4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
33 config MACH_SUNXI_H3_H5
37 select SUNXI_GEN_SUN6I
41 prompt "Sunxi SoC Variant"
45 bool "sun4i (Allwinner A10)"
47 select ARM_CORTEX_CPU_IS_UP
48 select SUNXI_GEN_SUN4I
52 bool "sun5i (Allwinner A13)"
54 select ARM_CORTEX_CPU_IS_UP
55 select SUNXI_GEN_SUN4I
59 bool "sun6i (Allwinner A31)"
61 select CPU_V7_HAS_NONSEC
62 select CPU_V7_HAS_VIRT
63 select ARCH_SUPPORT_PSCI
64 select SUNXI_GEN_SUN6I
66 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
69 bool "sun7i (Allwinner A20)"
71 select CPU_V7_HAS_NONSEC
72 select CPU_V7_HAS_VIRT
73 select ARCH_SUPPORT_PSCI
74 select SUNXI_GEN_SUN4I
76 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
79 bool "sun8i (Allwinner A23)"
81 select CPU_V7_HAS_NONSEC
82 select CPU_V7_HAS_VIRT
83 select ARCH_SUPPORT_PSCI
84 select SUNXI_GEN_SUN6I
86 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
89 bool "sun8i (Allwinner A33)"
91 select CPU_V7_HAS_NONSEC
92 select CPU_V7_HAS_VIRT
93 select ARCH_SUPPORT_PSCI
94 select SUNXI_GEN_SUN6I
96 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
98 config MACH_SUN8I_A83T
99 bool "sun8i (Allwinner A83T)"
101 select SUNXI_GEN_SUN6I
105 bool "sun8i (Allwinner H3)"
107 select CPU_V7_HAS_NONSEC
108 select CPU_V7_HAS_VIRT
109 select ARCH_SUPPORT_PSCI
110 select MACH_SUNXI_H3_H5
111 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
113 config MACH_SUN8I_R40
114 bool "sun8i (Allwinner R40)"
116 select CPU_V7_HAS_NONSEC
117 select CPU_V7_HAS_VIRT
118 select ARCH_SUPPORT_PSCI
119 select SUNXI_GEN_SUN6I
122 config MACH_SUN8I_V3S
123 bool "sun8i (Allwinner V3s)"
125 select CPU_V7_HAS_NONSEC
126 select CPU_V7_HAS_VIRT
127 select ARCH_SUPPORT_PSCI
128 select SUNXI_GEN_SUN6I
129 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
132 bool "sun9i (Allwinner A80)"
134 select SUNXI_HIGH_SRAM
135 select SUNXI_GEN_SUN6I
139 bool "sun50i (Allwinner A64)"
143 select SUNXI_GEN_SUN6I
144 select SUNXI_HIGH_SRAM
147 config MACH_SUN50I_H5
148 bool "sun50i (Allwinner H5)"
150 select MACH_SUNXI_H3_H5
151 select SUNXI_HIGH_SRAM
155 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
158 default y if MACH_SUN8I_A23
159 default y if MACH_SUN8I_A33
160 default y if MACH_SUN8I_A83T
161 default y if MACH_SUNXI_H3_H5
162 default y if MACH_SUN8I_R40
163 default y if MACH_SUN8I_V3S
165 config RESERVE_ALLWINNER_BOOT0_HEADER
166 bool "reserve space for Allwinner boot0 header"
167 select ENABLE_ARM_SOC_BOOT0_HOOK
169 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
170 filled with magic values post build. The Allwinner provided boot0
171 blob relies on this information to load and execute U-Boot.
172 Only needed on 64-bit Allwinner boards so far when using boot0.
174 config ARM_BOOT_HOOK_RMR
178 select ENABLE_ARM_SOC_BOOT0_HOOK
180 Insert some ARM32 code at the very beginning of the U-Boot binary
181 which uses an RMR register write to bring the core into AArch64 mode.
182 The very first instruction acts as a switch, since it's carefully
183 chosen to be a NOP in one mode and a branch in the other, so the
184 code would only be executed if not already in AArch64.
185 This allows both the SPL and the U-Boot proper to be entered in
186 either mode and switch to AArch64 if needed.
189 int "sunxi dram type"
190 depends on MACH_SUN8I_A83T
193 Set the dram type, 3: DDR3, 7: LPDDR3
196 int "sunxi dram clock speed"
197 default 792 if MACH_SUN9I
198 default 648 if MACH_SUN8I_R40
199 default 312 if MACH_SUN6I || MACH_SUN8I
200 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
201 default 672 if MACH_SUN50I
203 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
204 must be a multiple of 24. For the sun9i (A80), the tested values
205 (for DDR3-1600) are 312 to 792.
207 if MACH_SUN5I || MACH_SUN7I
209 int "sunxi mbus clock speed"
212 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
217 int "sunxi dram zq value"
218 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
219 default 127 if MACH_SUN7I
220 default 3881979 if MACH_SUN8I_R40
221 default 4145117 if MACH_SUN9I
222 default 3881915 if MACH_SUN50I
224 Set the dram zq value.
227 bool "sunxi dram odt enable"
228 default n if !MACH_SUN8I_A23
229 default y if MACH_SUN8I_A23
230 default y if MACH_SUN8I_R40
231 default y if MACH_SUN50I
233 Select this to enable dram odt (on die termination).
235 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
237 int "sunxi dram emr1 value"
238 default 0 if MACH_SUN4I
239 default 4 if MACH_SUN5I || MACH_SUN7I
241 Set the dram controller emr1 value.
244 hex "sunxi dram tpr3 value"
247 Set the dram controller tpr3 parameter. This parameter configures
248 the delay on the command lane and also phase shifts, which are
249 applied for sampling incoming read data. The default value 0
250 means that no phase/delay adjustments are necessary. Properly
251 configuring this parameter increases reliability at high DRAM
254 config DRAM_DQS_GATING_DELAY
255 hex "sunxi dram dqs_gating_delay value"
258 Set the dram controller dqs_gating_delay parmeter. Each byte
259 encodes the DQS gating delay for each byte lane. The delay
260 granularity is 1/4 cycle. For example, the value 0x05060606
261 means that the delay is 5 quarter-cycles for one lane (1.25
262 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
263 The default value 0 means autodetection. The results of hardware
264 autodetection are not very reliable and depend on the chip
265 temperature (sometimes producing different results on cold start
266 and warm reboot). But the accuracy of hardware autodetection
267 is usually good enough, unless running at really high DRAM
268 clocks speeds (up to 600MHz). If unsure, keep as 0.
271 prompt "sunxi dram timings"
272 default DRAM_TIMINGS_VENDOR_MAGIC
274 Select the timings of the DDR3 chips.
276 config DRAM_TIMINGS_VENDOR_MAGIC
277 bool "Magic vendor timings from Android"
279 The same DRAM timings as in the Allwinner boot0 bootloader.
281 config DRAM_TIMINGS_DDR3_1066F_1333H
282 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
284 Use the timings of the standard JEDEC DDR3-1066F speed bin for
285 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
286 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
287 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
288 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
289 that down binning to DDR3-1066F is supported (because DDR3-1066F
290 uses a bit faster timings than DDR3-1333H).
292 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
293 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
295 Use the timings of the slowest possible JEDEC speed bin for the
296 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
297 DDR3-800E, DDR3-1066G or DDR3-1333J.
304 config DRAM_ODT_CORRECTION
305 int "sunxi dram odt correction value"
308 Set the dram odt correction value (range -255 - 255). In allwinner
309 fex files, this option is found in bits 8-15 of the u32 odt_en variable
310 in the [dram] section. When bit 31 of the odt_en variable is set
311 then the correction is negative. Usually the value for this is 0.
315 default 1008000000 if MACH_SUN4I
316 default 1008000000 if MACH_SUN5I
317 default 1008000000 if MACH_SUN6I
318 default 912000000 if MACH_SUN7I
319 default 1008000000 if MACH_SUN8I
320 default 1008000000 if MACH_SUN9I
321 default 816000000 if MACH_SUN50I
323 config SYS_CONFIG_NAME
324 default "sun4i" if MACH_SUN4I
325 default "sun5i" if MACH_SUN5I
326 default "sun6i" if MACH_SUN6I
327 default "sun7i" if MACH_SUN7I
328 default "sun8i" if MACH_SUN8I
329 default "sun9i" if MACH_SUN9I
330 default "sun50i" if MACH_SUN50I
339 bool "UART0 on MicroSD breakout board"
342 Repurpose the SD card slot for getting access to the UART0 serial
343 console. Primarily useful only for low level u-boot debugging on
344 tablets, where normal UART0 is difficult to access and requires
345 device disassembly and/or soldering. As the SD card can't be used
346 at the same time, the system can be only booted in the FEL mode.
347 Only enable this if you really know what you are doing.
349 config OLD_SUNXI_KERNEL_COMPAT
350 bool "Enable workarounds for booting old kernels"
353 Set this to enable various workarounds for old kernels, this results in
354 sub-optimal settings for newer kernels, only enable if needed.
357 string "MAC power pin"
360 Set the pin used to power the MAC. This takes a string in the format
361 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
364 string "Card detect pin for mmc0"
365 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
368 Set the card detect pin for mmc0, leave empty to not use cd. This
369 takes a string in the format understood by sunxi_name_to_gpio, e.g.
370 PH1 for pin 1 of port H.
373 string "Card detect pin for mmc1"
376 See MMC0_CD_PIN help text.
379 string "Card detect pin for mmc2"
382 See MMC0_CD_PIN help text.
385 string "Card detect pin for mmc3"
388 See MMC0_CD_PIN help text.
391 string "Pins for mmc1"
394 Set the pins used for mmc1, when applicable. This takes a string in the
395 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
398 string "Pins for mmc2"
401 See MMC1_PINS help text.
404 string "Pins for mmc3"
407 See MMC1_PINS help text.
409 config MMC_SUNXI_SLOT_EXTRA
410 int "mmc extra slot number"
413 sunxi builds always enable mmc0, some boards also have a second sdcard
414 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
417 config INITIAL_USB_SCAN_DELAY
418 int "delay initial usb scan by x ms to allow builtin devices to init"
421 Some boards have on board usb devices which need longer than the
422 USB spec's 1 second to connect from board powerup. Set this config
423 option to a non 0 value to add an extra delay before the first usb
427 string "Vbus enable pin for usb0 (otg)"
430 Set the Vbus enable pin for usb0 (otg). This takes a string in the
431 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
434 string "Vbus detect pin for usb0 (otg)"
437 Set the Vbus detect pin for usb0 (otg). This takes a string in the
438 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
441 string "ID detect pin for usb0 (otg)"
444 Set the ID detect pin for usb0 (otg). This takes a string in the
445 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
448 string "Vbus enable pin for usb1 (ehci0)"
449 default "PH6" if MACH_SUN4I || MACH_SUN7I
450 default "PH27" if MACH_SUN6I
452 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
453 a string in the format understood by sunxi_name_to_gpio, e.g.
454 PH1 for pin 1 of port H.
457 string "Vbus enable pin for usb2 (ehci1)"
458 default "PH3" if MACH_SUN4I || MACH_SUN7I
459 default "PH24" if MACH_SUN6I
461 See USB1_VBUS_PIN help text.
464 string "Vbus enable pin for usb3 (ehci2)"
467 See USB1_VBUS_PIN help text.
470 bool "Enable I2C/TWI controller 0"
471 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
472 default n if MACH_SUN6I || MACH_SUN8I
475 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
476 its clock and setting up the bus. This is especially useful on devices
477 with slaves connected to the bus or with pins exposed through e.g. an
478 expansion port/header.
481 bool "Enable I2C/TWI controller 1"
485 See I2C0_ENABLE help text.
488 bool "Enable I2C/TWI controller 2"
492 See I2C0_ENABLE help text.
494 if MACH_SUN6I || MACH_SUN7I
496 bool "Enable I2C/TWI controller 3"
500 See I2C0_ENABLE help text.
505 bool "Enable the PRCM I2C/TWI controller"
506 # This is used for the pmic on H3
507 default y if SY8106A_POWER
510 Set this to y to enable the I2C controller which is part of the PRCM.
515 bool "Enable I2C/TWI controller 4"
519 See I2C0_ENABLE help text.
523 bool "Enable support for gpio-s on axp PMICs"
526 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
529 bool "Enable graphical uboot console on HDMI, LCD or VGA"
530 depends on !MACH_SUN8I_A83T
531 depends on !MACH_SUNXI_H3_H5
532 depends on !MACH_SUN8I_R40
533 depends on !MACH_SUN8I_V3S
534 depends on !MACH_SUN9I
535 depends on !MACH_SUN50I
538 Say Y here to add support for using a cfb console on the HDMI, LCD
539 or VGA output found on most sunxi devices. See doc/README.video for
540 info on how to select the video output and mode.
543 bool "HDMI output support"
544 depends on VIDEO && !MACH_SUN8I
547 Say Y here to add support for outputting video over HDMI.
550 bool "VGA output support"
551 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
554 Say Y here to add support for outputting video over VGA.
556 config VIDEO_VGA_VIA_LCD
557 bool "VGA via LCD controller support"
558 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
561 Say Y here to add support for external DACs connected to the parallel
562 LCD interface driving a VGA connector, such as found on the
565 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
566 bool "Force sync active high for VGA via LCD controller support"
567 depends on VIDEO_VGA_VIA_LCD
570 Say Y here if you've a board which uses opendrain drivers for the vga
571 hsync and vsync signals. Opendrain drivers cannot generate steep enough
572 positive edges for a stable video output, so on boards with opendrain
573 drivers the sync signals must always be active high.
575 config VIDEO_VGA_EXTERNAL_DAC_EN
576 string "LCD panel power enable pin"
577 depends on VIDEO_VGA_VIA_LCD
580 Set the enable pin for the external VGA DAC. This takes a string in the
581 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
583 config VIDEO_COMPOSITE
584 bool "Composite video output support"
585 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
588 Say Y here to add support for outputting composite video.
590 config VIDEO_LCD_MODE
591 string "LCD panel timing details"
595 LCD panel timing details string, leave empty if there is no LCD panel.
596 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
597 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
598 Also see: http://linux-sunxi.org/LCD
600 config VIDEO_LCD_DCLK_PHASE
601 int "LCD panel display clock phase"
605 Select LCD panel display clock phase shift, range 0-3.
607 config VIDEO_LCD_POWER
608 string "LCD panel power enable pin"
612 Set the power enable pin for the LCD panel. This takes a string in the
613 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
615 config VIDEO_LCD_RESET
616 string "LCD panel reset pin"
620 Set the reset pin for the LCD panel. This takes a string in the format
621 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
623 config VIDEO_LCD_BL_EN
624 string "LCD panel backlight enable pin"
628 Set the backlight enable pin for the LCD panel. This takes a string in the
629 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
632 config VIDEO_LCD_BL_PWM
633 string "LCD panel backlight pwm pin"
637 Set the backlight pwm pin for the LCD panel. This takes a string in the
638 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
640 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
641 bool "LCD panel backlight pwm is inverted"
645 Set this if the backlight pwm output is active low.
647 config VIDEO_LCD_PANEL_I2C
648 bool "LCD panel needs to be configured via i2c"
653 Say y here if the LCD panel needs to be configured via i2c. This
654 will add a bitbang i2c controller using gpios to talk to the LCD.
656 config VIDEO_LCD_PANEL_I2C_SDA
657 string "LCD panel i2c interface SDA pin"
658 depends on VIDEO_LCD_PANEL_I2C
661 Set the SDA pin for the LCD i2c interface. This takes a string in the
662 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
664 config VIDEO_LCD_PANEL_I2C_SCL
665 string "LCD panel i2c interface SCL pin"
666 depends on VIDEO_LCD_PANEL_I2C
669 Set the SCL pin for the LCD i2c interface. This takes a string in the
670 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
673 # Note only one of these may be selected at a time! But hidden choices are
674 # not supported by Kconfig
675 config VIDEO_LCD_IF_PARALLEL
678 config VIDEO_LCD_IF_LVDS
686 bool "Display Engine 2 video driver"
692 Say y here if you want to build DE2 video driver which is present on
693 newer SoCs. Currently only HDMI output is supported.
697 prompt "LCD panel support"
700 Select which type of LCD panel to support.
702 config VIDEO_LCD_PANEL_PARALLEL
703 bool "Generic parallel interface LCD panel"
704 select VIDEO_LCD_IF_PARALLEL
706 config VIDEO_LCD_PANEL_LVDS
707 bool "Generic lvds interface LCD panel"
708 select VIDEO_LCD_IF_LVDS
710 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
711 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
712 select VIDEO_LCD_SSD2828
713 select VIDEO_LCD_IF_PARALLEL
715 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
717 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
718 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
719 select VIDEO_LCD_ANX9804
720 select VIDEO_LCD_IF_PARALLEL
721 select VIDEO_LCD_PANEL_I2C
723 Select this for eDP LCD panels with 4 lanes running at 1.62G,
724 connected via an ANX9804 bridge chip.
726 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
727 bool "Hitachi tx18d42vm LCD panel"
728 select VIDEO_LCD_HITACHI_TX18D42VM
729 select VIDEO_LCD_IF_LVDS
731 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
733 config VIDEO_LCD_TL059WV5C0
734 bool "tl059wv5c0 LCD panel"
735 select VIDEO_LCD_PANEL_I2C
736 select VIDEO_LCD_IF_PARALLEL
738 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
739 Aigo M60/M608/M606 tablets.
744 string "SATA power pin"
747 Set the pins used to power the SATA. This takes a string in the
748 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
752 int "GMAC Transmit Clock Delay Chain"
755 Set the GMAC Transmit Clock Delay Chain value.
757 config SPL_STACK_R_ADDR
758 default 0x4fe00000 if MACH_SUN4I
759 default 0x4fe00000 if MACH_SUN5I
760 default 0x4fe00000 if MACH_SUN6I
761 default 0x4fe00000 if MACH_SUN7I
762 default 0x4fe00000 if MACH_SUN8I
763 default 0x2fe00000 if MACH_SUN9I
764 default 0x4fe00000 if MACH_SUN50I