4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
65 prompt "Sunxi SoC Variant"
69 bool "sun4i (Allwinner A10)"
71 select ARM_CORTEX_CPU_IS_UP
72 select SUNXI_GEN_SUN4I
77 bool "sun5i (Allwinner A13)"
79 select ARM_CORTEX_CPU_IS_UP
80 select SUNXI_GEN_SUN4I
84 bool "sun6i (Allwinner A31)"
86 select CPU_V7_HAS_NONSEC
87 select CPU_V7_HAS_VIRT
88 select ARCH_SUPPORT_PSCI
89 select SUNXI_GEN_SUN6I
91 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
95 bool "sun7i (Allwinner A20)"
97 select CPU_V7_HAS_NONSEC
98 select CPU_V7_HAS_VIRT
99 select ARCH_SUPPORT_PSCI
100 select SUNXI_GEN_SUN4I
102 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
105 config MACH_SUN8I_A23
106 bool "sun8i (Allwinner A23)"
108 select CPU_V7_HAS_NONSEC
109 select CPU_V7_HAS_VIRT
110 select ARCH_SUPPORT_PSCI
111 select SUNXI_GEN_SUN6I
113 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
116 config MACH_SUN8I_A33
117 bool "sun8i (Allwinner A33)"
119 select CPU_V7_HAS_NONSEC
120 select CPU_V7_HAS_VIRT
121 select ARCH_SUPPORT_PSCI
122 select SUNXI_GEN_SUN6I
124 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
126 config MACH_SUN8I_A83T
127 bool "sun8i (Allwinner A83T)"
129 select SUNXI_GEN_SUN6I
133 bool "sun8i (Allwinner H3)"
135 select CPU_V7_HAS_NONSEC
136 select CPU_V7_HAS_VIRT
137 select ARCH_SUPPORT_PSCI
138 select MACH_SUNXI_H3_H5
139 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
142 config MACH_SUN8I_R40
143 bool "sun8i (Allwinner R40)"
145 select CPU_V7_HAS_NONSEC
146 select CPU_V7_HAS_VIRT
147 select ARCH_SUPPORT_PSCI
148 select SUNXI_GEN_SUN6I
151 select SUNXI_DRAM_DW_32BIT
153 config MACH_SUN8I_V3S
154 bool "sun8i (Allwinner V3s)"
156 select CPU_V7_HAS_NONSEC
157 select CPU_V7_HAS_VIRT
158 select ARCH_SUPPORT_PSCI
159 select SUNXI_GEN_SUN6I
161 select SUNXI_DRAM_DW_16BIT
163 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
166 bool "sun9i (Allwinner A80)"
168 select SUNXI_HIGH_SRAM
169 select SUNXI_GEN_SUN6I
173 bool "sun50i (Allwinner A64)"
177 select SUNXI_GEN_SUN6I
178 select SUNXI_HIGH_SRAM
181 select SUNXI_DRAM_DW_32BIT
185 config MACH_SUN50I_H5
186 bool "sun50i (Allwinner H5)"
188 select MACH_SUNXI_H3_H5
189 select SUNXI_HIGH_SRAM
195 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
198 default y if MACH_SUN8I_A23
199 default y if MACH_SUN8I_A33
200 default y if MACH_SUN8I_A83T
201 default y if MACH_SUNXI_H3_H5
202 default y if MACH_SUN8I_R40
203 default y if MACH_SUN8I_V3S
205 config RESERVE_ALLWINNER_BOOT0_HEADER
206 bool "reserve space for Allwinner boot0 header"
207 select ENABLE_ARM_SOC_BOOT0_HOOK
209 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
210 filled with magic values post build. The Allwinner provided boot0
211 blob relies on this information to load and execute U-Boot.
212 Only needed on 64-bit Allwinner boards so far when using boot0.
214 config ARM_BOOT_HOOK_RMR
218 select ENABLE_ARM_SOC_BOOT0_HOOK
220 Insert some ARM32 code at the very beginning of the U-Boot binary
221 which uses an RMR register write to bring the core into AArch64 mode.
222 The very first instruction acts as a switch, since it's carefully
223 chosen to be a NOP in one mode and a branch in the other, so the
224 code would only be executed if not already in AArch64.
225 This allows both the SPL and the U-Boot proper to be entered in
226 either mode and switch to AArch64 if needed.
229 config SUNXI_DRAM_DDR3
232 config SUNXI_DRAM_DDR2
235 config SUNXI_DRAM_LPDDR3
239 prompt "DRAM Type and Timing"
240 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
241 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
243 config SUNXI_DRAM_DDR3_1333
245 select SUNXI_DRAM_DDR3
246 depends on !MACH_SUN8I_V3S
248 This option is the original only supported memory type, which suits
249 many H3/H5/A64 boards available now.
251 config SUNXI_DRAM_LPDDR3_STOCK
252 bool "LPDDR3 with Allwinner stock configuration"
253 select SUNXI_DRAM_LPDDR3
255 This option is the LPDDR3 timing used by the stock boot0 by
258 config SUNXI_DRAM_DDR2_V3S
259 bool "DDR2 found in V3s chip"
260 select SUNXI_DRAM_DDR2
261 depends on MACH_SUN8I_V3S
263 This option is only for the DDR2 memory chip which is co-packaged in
270 int "sunxi dram type"
271 depends on MACH_SUN8I_A83T
274 Set the dram type, 3: DDR3, 7: LPDDR3
277 int "sunxi dram clock speed"
278 default 792 if MACH_SUN9I
279 default 648 if MACH_SUN8I_R40
280 default 312 if MACH_SUN6I || MACH_SUN8I
281 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
283 default 672 if MACH_SUN50I
285 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
286 must be a multiple of 24. For the sun9i (A80), the tested values
287 (for DDR3-1600) are 312 to 792.
289 if MACH_SUN5I || MACH_SUN7I
291 int "sunxi mbus clock speed"
294 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
299 int "sunxi dram zq value"
300 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
301 default 127 if MACH_SUN7I
302 default 14779 if MACH_SUN8I_V3S
303 default 3881979 if MACH_SUN8I_R40
304 default 4145117 if MACH_SUN9I
305 default 3881915 if MACH_SUN50I
307 Set the dram zq value.
310 bool "sunxi dram odt enable"
311 default n if !MACH_SUN8I_A23
312 default y if MACH_SUN8I_A23
313 default y if MACH_SUN8I_R40
314 default y if MACH_SUN50I
316 Select this to enable dram odt (on die termination).
318 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
320 int "sunxi dram emr1 value"
321 default 0 if MACH_SUN4I
322 default 4 if MACH_SUN5I || MACH_SUN7I
324 Set the dram controller emr1 value.
327 hex "sunxi dram tpr3 value"
330 Set the dram controller tpr3 parameter. This parameter configures
331 the delay on the command lane and also phase shifts, which are
332 applied for sampling incoming read data. The default value 0
333 means that no phase/delay adjustments are necessary. Properly
334 configuring this parameter increases reliability at high DRAM
337 config DRAM_DQS_GATING_DELAY
338 hex "sunxi dram dqs_gating_delay value"
341 Set the dram controller dqs_gating_delay parmeter. Each byte
342 encodes the DQS gating delay for each byte lane. The delay
343 granularity is 1/4 cycle. For example, the value 0x05060606
344 means that the delay is 5 quarter-cycles for one lane (1.25
345 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
346 The default value 0 means autodetection. The results of hardware
347 autodetection are not very reliable and depend on the chip
348 temperature (sometimes producing different results on cold start
349 and warm reboot). But the accuracy of hardware autodetection
350 is usually good enough, unless running at really high DRAM
351 clocks speeds (up to 600MHz). If unsure, keep as 0.
354 prompt "sunxi dram timings"
355 default DRAM_TIMINGS_VENDOR_MAGIC
357 Select the timings of the DDR3 chips.
359 config DRAM_TIMINGS_VENDOR_MAGIC
360 bool "Magic vendor timings from Android"
362 The same DRAM timings as in the Allwinner boot0 bootloader.
364 config DRAM_TIMINGS_DDR3_1066F_1333H
365 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
367 Use the timings of the standard JEDEC DDR3-1066F speed bin for
368 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
369 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
370 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
371 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
372 that down binning to DDR3-1066F is supported (because DDR3-1066F
373 uses a bit faster timings than DDR3-1333H).
375 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
376 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
378 Use the timings of the slowest possible JEDEC speed bin for the
379 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
380 DDR3-800E, DDR3-1066G or DDR3-1333J.
387 config DRAM_ODT_CORRECTION
388 int "sunxi dram odt correction value"
391 Set the dram odt correction value (range -255 - 255). In allwinner
392 fex files, this option is found in bits 8-15 of the u32 odt_en variable
393 in the [dram] section. When bit 31 of the odt_en variable is set
394 then the correction is negative. Usually the value for this is 0.
398 default 1008000000 if MACH_SUN4I
399 default 1008000000 if MACH_SUN5I
400 default 1008000000 if MACH_SUN6I
401 default 912000000 if MACH_SUN7I
402 default 1008000000 if MACH_SUN8I
403 default 1008000000 if MACH_SUN9I
404 default 816000000 if MACH_SUN50I
406 config SYS_CONFIG_NAME
407 default "sun4i" if MACH_SUN4I
408 default "sun5i" if MACH_SUN5I
409 default "sun6i" if MACH_SUN6I
410 default "sun7i" if MACH_SUN7I
411 default "sun8i" if MACH_SUN8I
412 default "sun9i" if MACH_SUN9I
413 default "sun50i" if MACH_SUN50I
422 bool "UART0 on MicroSD breakout board"
425 Repurpose the SD card slot for getting access to the UART0 serial
426 console. Primarily useful only for low level u-boot debugging on
427 tablets, where normal UART0 is difficult to access and requires
428 device disassembly and/or soldering. As the SD card can't be used
429 at the same time, the system can be only booted in the FEL mode.
430 Only enable this if you really know what you are doing.
432 config OLD_SUNXI_KERNEL_COMPAT
433 bool "Enable workarounds for booting old kernels"
436 Set this to enable various workarounds for old kernels, this results in
437 sub-optimal settings for newer kernels, only enable if needed.
440 string "MAC power pin"
443 Set the pin used to power the MAC. This takes a string in the format
444 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
447 string "Card detect pin for mmc0"
448 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
451 Set the card detect pin for mmc0, leave empty to not use cd. This
452 takes a string in the format understood by sunxi_name_to_gpio, e.g.
453 PH1 for pin 1 of port H.
456 string "Card detect pin for mmc1"
459 See MMC0_CD_PIN help text.
462 string "Card detect pin for mmc2"
465 See MMC0_CD_PIN help text.
468 string "Card detect pin for mmc3"
471 See MMC0_CD_PIN help text.
474 string "Pins for mmc1"
477 Set the pins used for mmc1, when applicable. This takes a string in the
478 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
481 string "Pins for mmc2"
484 See MMC1_PINS help text.
487 string "Pins for mmc3"
490 See MMC1_PINS help text.
492 config MMC_SUNXI_SLOT_EXTRA
493 int "mmc extra slot number"
496 sunxi builds always enable mmc0, some boards also have a second sdcard
497 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
500 config INITIAL_USB_SCAN_DELAY
501 int "delay initial usb scan by x ms to allow builtin devices to init"
504 Some boards have on board usb devices which need longer than the
505 USB spec's 1 second to connect from board powerup. Set this config
506 option to a non 0 value to add an extra delay before the first usb
510 string "Vbus enable pin for usb0 (otg)"
513 Set the Vbus enable pin for usb0 (otg). This takes a string in the
514 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
517 string "Vbus detect pin for usb0 (otg)"
520 Set the Vbus detect pin for usb0 (otg). This takes a string in the
521 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
524 string "ID detect pin for usb0 (otg)"
527 Set the ID detect pin for usb0 (otg). This takes a string in the
528 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
531 string "Vbus enable pin for usb1 (ehci0)"
532 default "PH6" if MACH_SUN4I || MACH_SUN7I
533 default "PH27" if MACH_SUN6I
535 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
536 a string in the format understood by sunxi_name_to_gpio, e.g.
537 PH1 for pin 1 of port H.
540 string "Vbus enable pin for usb2 (ehci1)"
541 default "PH3" if MACH_SUN4I || MACH_SUN7I
542 default "PH24" if MACH_SUN6I
544 See USB1_VBUS_PIN help text.
547 string "Vbus enable pin for usb3 (ehci2)"
550 See USB1_VBUS_PIN help text.
553 bool "Enable I2C/TWI controller 0"
554 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
555 default n if MACH_SUN6I || MACH_SUN8I
558 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
559 its clock and setting up the bus. This is especially useful on devices
560 with slaves connected to the bus or with pins exposed through e.g. an
561 expansion port/header.
564 bool "Enable I2C/TWI controller 1"
568 See I2C0_ENABLE help text.
571 bool "Enable I2C/TWI controller 2"
575 See I2C0_ENABLE help text.
577 if MACH_SUN6I || MACH_SUN7I
579 bool "Enable I2C/TWI controller 3"
583 See I2C0_ENABLE help text.
588 bool "Enable the PRCM I2C/TWI controller"
589 # This is used for the pmic on H3
590 default y if SY8106A_POWER
593 Set this to y to enable the I2C controller which is part of the PRCM.
598 bool "Enable I2C/TWI controller 4"
602 See I2C0_ENABLE help text.
606 bool "Enable support for gpio-s on axp PMICs"
609 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
612 bool "Enable graphical uboot console on HDMI, LCD or VGA"
613 depends on !MACH_SUN8I_A83T
614 depends on !MACH_SUNXI_H3_H5
615 depends on !MACH_SUN8I_R40
616 depends on !MACH_SUN8I_V3S
617 depends on !MACH_SUN9I
618 depends on !MACH_SUN50I
621 Say Y here to add support for using a cfb console on the HDMI, LCD
622 or VGA output found on most sunxi devices. See doc/README.video for
623 info on how to select the video output and mode.
626 bool "HDMI output support"
627 depends on VIDEO && !MACH_SUN8I
630 Say Y here to add support for outputting video over HDMI.
633 bool "VGA output support"
634 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
637 Say Y here to add support for outputting video over VGA.
639 config VIDEO_VGA_VIA_LCD
640 bool "VGA via LCD controller support"
641 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
644 Say Y here to add support for external DACs connected to the parallel
645 LCD interface driving a VGA connector, such as found on the
648 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
649 bool "Force sync active high for VGA via LCD controller support"
650 depends on VIDEO_VGA_VIA_LCD
653 Say Y here if you've a board which uses opendrain drivers for the vga
654 hsync and vsync signals. Opendrain drivers cannot generate steep enough
655 positive edges for a stable video output, so on boards with opendrain
656 drivers the sync signals must always be active high.
658 config VIDEO_VGA_EXTERNAL_DAC_EN
659 string "LCD panel power enable pin"
660 depends on VIDEO_VGA_VIA_LCD
663 Set the enable pin for the external VGA DAC. This takes a string in the
664 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
666 config VIDEO_COMPOSITE
667 bool "Composite video output support"
668 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
671 Say Y here to add support for outputting composite video.
673 config VIDEO_LCD_MODE
674 string "LCD panel timing details"
678 LCD panel timing details string, leave empty if there is no LCD panel.
679 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
680 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
681 Also see: http://linux-sunxi.org/LCD
683 config VIDEO_LCD_DCLK_PHASE
684 int "LCD panel display clock phase"
688 Select LCD panel display clock phase shift, range 0-3.
690 config VIDEO_LCD_POWER
691 string "LCD panel power enable pin"
695 Set the power enable pin for the LCD panel. This takes a string in the
696 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
698 config VIDEO_LCD_RESET
699 string "LCD panel reset pin"
703 Set the reset pin for the LCD panel. This takes a string in the format
704 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
706 config VIDEO_LCD_BL_EN
707 string "LCD panel backlight enable pin"
711 Set the backlight enable pin for the LCD panel. This takes a string in the
712 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
715 config VIDEO_LCD_BL_PWM
716 string "LCD panel backlight pwm pin"
720 Set the backlight pwm pin for the LCD panel. This takes a string in the
721 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
723 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
724 bool "LCD panel backlight pwm is inverted"
728 Set this if the backlight pwm output is active low.
730 config VIDEO_LCD_PANEL_I2C
731 bool "LCD panel needs to be configured via i2c"
736 Say y here if the LCD panel needs to be configured via i2c. This
737 will add a bitbang i2c controller using gpios to talk to the LCD.
739 config VIDEO_LCD_PANEL_I2C_SDA
740 string "LCD panel i2c interface SDA pin"
741 depends on VIDEO_LCD_PANEL_I2C
744 Set the SDA pin for the LCD i2c interface. This takes a string in the
745 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
747 config VIDEO_LCD_PANEL_I2C_SCL
748 string "LCD panel i2c interface SCL pin"
749 depends on VIDEO_LCD_PANEL_I2C
752 Set the SCL pin for the LCD i2c interface. This takes a string in the
753 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
756 # Note only one of these may be selected at a time! But hidden choices are
757 # not supported by Kconfig
758 config VIDEO_LCD_IF_PARALLEL
761 config VIDEO_LCD_IF_LVDS
769 bool "Display Engine 2 video driver"
775 Say y here if you want to build DE2 video driver which is present on
776 newer SoCs. Currently only HDMI output is supported.
780 prompt "LCD panel support"
783 Select which type of LCD panel to support.
785 config VIDEO_LCD_PANEL_PARALLEL
786 bool "Generic parallel interface LCD panel"
787 select VIDEO_LCD_IF_PARALLEL
789 config VIDEO_LCD_PANEL_LVDS
790 bool "Generic lvds interface LCD panel"
791 select VIDEO_LCD_IF_LVDS
793 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
794 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
795 select VIDEO_LCD_SSD2828
796 select VIDEO_LCD_IF_PARALLEL
798 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
800 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
801 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
802 select VIDEO_LCD_ANX9804
803 select VIDEO_LCD_IF_PARALLEL
804 select VIDEO_LCD_PANEL_I2C
806 Select this for eDP LCD panels with 4 lanes running at 1.62G,
807 connected via an ANX9804 bridge chip.
809 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
810 bool "Hitachi tx18d42vm LCD panel"
811 select VIDEO_LCD_HITACHI_TX18D42VM
812 select VIDEO_LCD_IF_LVDS
814 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
816 config VIDEO_LCD_TL059WV5C0
817 bool "tl059wv5c0 LCD panel"
818 select VIDEO_LCD_PANEL_I2C
819 select VIDEO_LCD_IF_PARALLEL
821 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
822 Aigo M60/M608/M606 tablets.
827 string "SATA power pin"
830 Set the pins used to power the SATA. This takes a string in the
831 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
835 int "GMAC Transmit Clock Delay Chain"
838 Set the GMAC Transmit Clock Delay Chain value.
840 config SPL_STACK_R_ADDR
841 default 0x4fe00000 if MACH_SUN4I
842 default 0x4fe00000 if MACH_SUN5I
843 default 0x4fe00000 if MACH_SUN6I
844 default 0x4fe00000 if MACH_SUN7I
845 default 0x4fe00000 if MACH_SUN8I
846 default 0x2fe00000 if MACH_SUN9I
847 default 0x4fe00000 if MACH_SUN50I