4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
10 bool "Allwinner sun6i internal P2WI controller"
12 If you say yes to this option, support will be included for the
13 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
15 The P2WI looks like an SMBus controller (which supports only byte
16 accesses), except that it only supports one slave device.
17 This interface is used to connect to specific PMIC devices (like the
23 Support for the PRCM (Power/Reset/Clock Management) unit available
26 config SUNXI_HIGH_SRAM
30 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
31 with the first SRAM region being located at address 0.
32 Some newer SoCs map the boot ROM at address 0 instead and move the
33 SRAM to 64KB, just behind the mask ROM.
34 Chips using the latter setup are supposed to select this option to
35 adjust the addresses accordingly.
37 # Note only one of these may be selected at a time! But hidden choices are
38 # not supported by Kconfig
39 config SUNXI_GEN_SUN4I
42 Select this for sunxi SoCs which have resets and clocks set up
43 as the original A10 (mach-sun4i).
45 config SUNXI_GEN_SUN6I
48 Select this for sunxi SoCs which have sun6i like periphery, like
49 separate ahb reset control registers, custom pmic bus, new style
55 Select this for sunxi SoCs which uses a DRAM controller like the
56 DesignWare controller used in H3, mainly SoCs after H3, which do
57 not have official open-source DRAM initialization code, but can
58 use modified H3 DRAM initialization code.
61 config SUNXI_DRAM_DW_16BIT
64 Select this for sunxi SoCs with DesignWare DRAM controller and
65 have only 16-bit memory buswidth.
67 config SUNXI_DRAM_DW_32BIT
70 Select this for sunxi SoCs with DesignWare DRAM controller with
71 32-bit memory buswidth.
74 config MACH_SUNXI_H3_H5
79 select SUNXI_DRAM_DW_32BIT
80 select SUNXI_GEN_SUN6I
84 prompt "Sunxi SoC Variant"
88 bool "sun4i (Allwinner A10)"
90 select ARM_CORTEX_CPU_IS_UP
91 select SUNXI_GEN_SUN4I
95 bool "sun5i (Allwinner A13)"
97 select ARM_CORTEX_CPU_IS_UP
98 select SUNXI_GEN_SUN4I
100 imply CONS_INDEX_2 if !DM_SERIAL
103 bool "sun6i (Allwinner A31)"
105 select CPU_V7_HAS_NONSEC
106 select CPU_V7_HAS_VIRT
107 select ARCH_SUPPORT_PSCI
110 select SUNXI_GEN_SUN6I
112 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
115 bool "sun7i (Allwinner A20)"
117 select CPU_V7_HAS_NONSEC
118 select CPU_V7_HAS_VIRT
119 select ARCH_SUPPORT_PSCI
120 select SUNXI_GEN_SUN4I
122 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
124 config MACH_SUN8I_A23
125 bool "sun8i (Allwinner A23)"
127 select CPU_V7_HAS_NONSEC
128 select CPU_V7_HAS_VIRT
129 select ARCH_SUPPORT_PSCI
130 select SUNXI_GEN_SUN6I
132 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
133 imply CONS_INDEX_5 if !DM_SERIAL
135 config MACH_SUN8I_A33
136 bool "sun8i (Allwinner A33)"
138 select CPU_V7_HAS_NONSEC
139 select CPU_V7_HAS_VIRT
140 select ARCH_SUPPORT_PSCI
141 select SUNXI_GEN_SUN6I
143 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
144 imply CONS_INDEX_5 if !DM_SERIAL
146 config MACH_SUN8I_A83T
147 bool "sun8i (Allwinner A83T)"
149 select SUNXI_GEN_SUN6I
150 select MMC_SUNXI_HAS_NEW_MODE
154 bool "sun8i (Allwinner H3)"
156 select CPU_V7_HAS_NONSEC
157 select CPU_V7_HAS_VIRT
158 select ARCH_SUPPORT_PSCI
159 select MACH_SUNXI_H3_H5
160 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
162 config MACH_SUN8I_R40
163 bool "sun8i (Allwinner R40)"
165 select CPU_V7_HAS_NONSEC
166 select CPU_V7_HAS_VIRT
167 select ARCH_SUPPORT_PSCI
168 select SUNXI_GEN_SUN6I
171 select SUNXI_DRAM_DW_32BIT
173 config MACH_SUN8I_V3S
174 bool "sun8i (Allwinner V3s)"
176 select CPU_V7_HAS_NONSEC
177 select CPU_V7_HAS_VIRT
178 select ARCH_SUPPORT_PSCI
179 select SUNXI_GEN_SUN6I
181 select SUNXI_DRAM_DW_16BIT
183 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
186 bool "sun9i (Allwinner A80)"
189 select SUNXI_HIGH_SRAM
190 select SUNXI_GEN_SUN6I
194 bool "sun50i (Allwinner A64)"
198 select SUNXI_GEN_SUN6I
199 select SUNXI_HIGH_SRAM
202 select SUNXI_DRAM_DW_32BIT
206 config MACH_SUN50I_H5
207 bool "sun50i (Allwinner H5)"
209 select MACH_SUNXI_H3_H5
210 select SUNXI_HIGH_SRAM
216 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
220 default y if MACH_SUN8I_A23
221 default y if MACH_SUN8I_A33
222 default y if MACH_SUN8I_A83T
223 default y if MACH_SUNXI_H3_H5
224 default y if MACH_SUN8I_R40
225 default y if MACH_SUN8I_V3S
227 config RESERVE_ALLWINNER_BOOT0_HEADER
228 bool "reserve space for Allwinner boot0 header"
229 select ENABLE_ARM_SOC_BOOT0_HOOK
231 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
232 filled with magic values post build. The Allwinner provided boot0
233 blob relies on this information to load and execute U-Boot.
234 Only needed on 64-bit Allwinner boards so far when using boot0.
236 config ARM_BOOT_HOOK_RMR
240 select ENABLE_ARM_SOC_BOOT0_HOOK
242 Insert some ARM32 code at the very beginning of the U-Boot binary
243 which uses an RMR register write to bring the core into AArch64 mode.
244 The very first instruction acts as a switch, since it's carefully
245 chosen to be a NOP in one mode and a branch in the other, so the
246 code would only be executed if not already in AArch64.
247 This allows both the SPL and the U-Boot proper to be entered in
248 either mode and switch to AArch64 if needed.
251 config SUNXI_DRAM_DDR3
254 config SUNXI_DRAM_DDR2
257 config SUNXI_DRAM_LPDDR3
261 prompt "DRAM Type and Timing"
262 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
263 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
265 config SUNXI_DRAM_DDR3_1333
267 select SUNXI_DRAM_DDR3
268 depends on !MACH_SUN8I_V3S
270 This option is the original only supported memory type, which suits
271 many H3/H5/A64 boards available now.
273 config SUNXI_DRAM_LPDDR3_STOCK
274 bool "LPDDR3 with Allwinner stock configuration"
275 select SUNXI_DRAM_LPDDR3
277 This option is the LPDDR3 timing used by the stock boot0 by
280 config SUNXI_DRAM_DDR2_V3S
281 bool "DDR2 found in V3s chip"
282 select SUNXI_DRAM_DDR2
283 depends on MACH_SUN8I_V3S
285 This option is only for the DDR2 memory chip which is co-packaged in
292 int "sunxi dram type"
293 depends on MACH_SUN8I_A83T
296 Set the dram type, 3: DDR3, 7: LPDDR3
299 int "sunxi dram clock speed"
300 default 792 if MACH_SUN9I
301 default 648 if MACH_SUN8I_R40
302 default 312 if MACH_SUN6I || MACH_SUN8I
303 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
305 default 672 if MACH_SUN50I
307 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
308 must be a multiple of 24. For the sun9i (A80), the tested values
309 (for DDR3-1600) are 312 to 792.
311 if MACH_SUN5I || MACH_SUN7I
313 int "sunxi mbus clock speed"
316 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
321 int "sunxi dram zq value"
322 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
323 default 127 if MACH_SUN7I
324 default 14779 if MACH_SUN8I_V3S
325 default 3881979 if MACH_SUN8I_R40
326 default 4145117 if MACH_SUN9I
327 default 3881915 if MACH_SUN50I
329 Set the dram zq value.
332 bool "sunxi dram odt enable"
333 default n if !MACH_SUN8I_A23
334 default y if MACH_SUN8I_A23
335 default y if MACH_SUN8I_R40
336 default y if MACH_SUN50I
338 Select this to enable dram odt (on die termination).
340 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
342 int "sunxi dram emr1 value"
343 default 0 if MACH_SUN4I
344 default 4 if MACH_SUN5I || MACH_SUN7I
346 Set the dram controller emr1 value.
349 hex "sunxi dram tpr3 value"
352 Set the dram controller tpr3 parameter. This parameter configures
353 the delay on the command lane and also phase shifts, which are
354 applied for sampling incoming read data. The default value 0
355 means that no phase/delay adjustments are necessary. Properly
356 configuring this parameter increases reliability at high DRAM
359 config DRAM_DQS_GATING_DELAY
360 hex "sunxi dram dqs_gating_delay value"
363 Set the dram controller dqs_gating_delay parmeter. Each byte
364 encodes the DQS gating delay for each byte lane. The delay
365 granularity is 1/4 cycle. For example, the value 0x05060606
366 means that the delay is 5 quarter-cycles for one lane (1.25
367 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
368 The default value 0 means autodetection. The results of hardware
369 autodetection are not very reliable and depend on the chip
370 temperature (sometimes producing different results on cold start
371 and warm reboot). But the accuracy of hardware autodetection
372 is usually good enough, unless running at really high DRAM
373 clocks speeds (up to 600MHz). If unsure, keep as 0.
376 prompt "sunxi dram timings"
377 default DRAM_TIMINGS_VENDOR_MAGIC
379 Select the timings of the DDR3 chips.
381 config DRAM_TIMINGS_VENDOR_MAGIC
382 bool "Magic vendor timings from Android"
384 The same DRAM timings as in the Allwinner boot0 bootloader.
386 config DRAM_TIMINGS_DDR3_1066F_1333H
387 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
389 Use the timings of the standard JEDEC DDR3-1066F speed bin for
390 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
391 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
392 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
393 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
394 that down binning to DDR3-1066F is supported (because DDR3-1066F
395 uses a bit faster timings than DDR3-1333H).
397 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
398 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
400 Use the timings of the slowest possible JEDEC speed bin for the
401 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
402 DDR3-800E, DDR3-1066G or DDR3-1333J.
409 config DRAM_ODT_CORRECTION
410 int "sunxi dram odt correction value"
413 Set the dram odt correction value (range -255 - 255). In allwinner
414 fex files, this option is found in bits 8-15 of the u32 odt_en variable
415 in the [dram] section. When bit 31 of the odt_en variable is set
416 then the correction is negative. Usually the value for this is 0.
420 default 1008000000 if MACH_SUN4I
421 default 1008000000 if MACH_SUN5I
422 default 1008000000 if MACH_SUN6I
423 default 912000000 if MACH_SUN7I
424 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
425 default 1008000000 if MACH_SUN8I
426 default 1008000000 if MACH_SUN9I
428 config SYS_CONFIG_NAME
429 default "sun4i" if MACH_SUN4I
430 default "sun5i" if MACH_SUN5I
431 default "sun6i" if MACH_SUN6I
432 default "sun7i" if MACH_SUN7I
433 default "sun8i" if MACH_SUN8I
434 default "sun9i" if MACH_SUN9I
435 default "sun50i" if MACH_SUN50I
444 bool "UART0 on MicroSD breakout board"
447 Repurpose the SD card slot for getting access to the UART0 serial
448 console. Primarily useful only for low level u-boot debugging on
449 tablets, where normal UART0 is difficult to access and requires
450 device disassembly and/or soldering. As the SD card can't be used
451 at the same time, the system can be only booted in the FEL mode.
452 Only enable this if you really know what you are doing.
454 config OLD_SUNXI_KERNEL_COMPAT
455 bool "Enable workarounds for booting old kernels"
458 Set this to enable various workarounds for old kernels, this results in
459 sub-optimal settings for newer kernels, only enable if needed.
462 string "MAC power pin"
465 Set the pin used to power the MAC. This takes a string in the format
466 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
469 string "Card detect pin for mmc0"
470 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
473 Set the card detect pin for mmc0, leave empty to not use cd. This
474 takes a string in the format understood by sunxi_name_to_gpio, e.g.
475 PH1 for pin 1 of port H.
478 string "Card detect pin for mmc1"
481 See MMC0_CD_PIN help text.
484 string "Card detect pin for mmc2"
487 See MMC0_CD_PIN help text.
490 string "Card detect pin for mmc3"
493 See MMC0_CD_PIN help text.
496 string "Pins for mmc1"
499 Set the pins used for mmc1, when applicable. This takes a string in the
500 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
503 string "Pins for mmc2"
506 See MMC1_PINS help text.
509 string "Pins for mmc3"
512 See MMC1_PINS help text.
514 config MMC_SUNXI_SLOT_EXTRA
515 int "mmc extra slot number"
518 sunxi builds always enable mmc0, some boards also have a second sdcard
519 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
522 config INITIAL_USB_SCAN_DELAY
523 int "delay initial usb scan by x ms to allow builtin devices to init"
526 Some boards have on board usb devices which need longer than the
527 USB spec's 1 second to connect from board powerup. Set this config
528 option to a non 0 value to add an extra delay before the first usb
532 string "Vbus enable pin for usb0 (otg)"
535 Set the Vbus enable pin for usb0 (otg). This takes a string in the
536 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
539 string "Vbus detect pin for usb0 (otg)"
542 Set the Vbus detect pin for usb0 (otg). This takes a string in the
543 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
546 string "ID detect pin for usb0 (otg)"
549 Set the ID detect pin for usb0 (otg). This takes a string in the
550 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
553 string "Vbus enable pin for usb1 (ehci0)"
554 default "PH6" if MACH_SUN4I || MACH_SUN7I
555 default "PH27" if MACH_SUN6I
557 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
558 a string in the format understood by sunxi_name_to_gpio, e.g.
559 PH1 for pin 1 of port H.
562 string "Vbus enable pin for usb2 (ehci1)"
563 default "PH3" if MACH_SUN4I || MACH_SUN7I
564 default "PH24" if MACH_SUN6I
566 See USB1_VBUS_PIN help text.
569 string "Vbus enable pin for usb3 (ehci2)"
572 See USB1_VBUS_PIN help text.
575 bool "Enable I2C/TWI controller 0"
576 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
577 default n if MACH_SUN6I || MACH_SUN8I
580 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
581 its clock and setting up the bus. This is especially useful on devices
582 with slaves connected to the bus or with pins exposed through e.g. an
583 expansion port/header.
586 bool "Enable I2C/TWI controller 1"
590 See I2C0_ENABLE help text.
593 bool "Enable I2C/TWI controller 2"
597 See I2C0_ENABLE help text.
599 if MACH_SUN6I || MACH_SUN7I
601 bool "Enable I2C/TWI controller 3"
605 See I2C0_ENABLE help text.
610 bool "Enable the PRCM I2C/TWI controller"
611 # This is used for the pmic on H3
612 default y if SY8106A_POWER
615 Set this to y to enable the I2C controller which is part of the PRCM.
620 bool "Enable I2C/TWI controller 4"
624 See I2C0_ENABLE help text.
628 bool "Enable support for gpio-s on axp PMICs"
631 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
634 bool "Enable graphical uboot console on HDMI, LCD or VGA"
635 depends on !MACH_SUN8I_A83T
636 depends on !MACH_SUNXI_H3_H5
637 depends on !MACH_SUN8I_R40
638 depends on !MACH_SUN8I_V3S
639 depends on !MACH_SUN9I
640 depends on !MACH_SUN50I
642 imply VIDEO_DT_SIMPLEFB
645 Say Y here to add support for using a cfb console on the HDMI, LCD
646 or VGA output found on most sunxi devices. See doc/README.video for
647 info on how to select the video output and mode.
650 bool "HDMI output support"
651 depends on VIDEO_SUNXI && !MACH_SUN8I
654 Say Y here to add support for outputting video over HDMI.
657 bool "VGA output support"
658 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
661 Say Y here to add support for outputting video over VGA.
663 config VIDEO_VGA_VIA_LCD
664 bool "VGA via LCD controller support"
665 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
668 Say Y here to add support for external DACs connected to the parallel
669 LCD interface driving a VGA connector, such as found on the
672 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
673 bool "Force sync active high for VGA via LCD controller support"
674 depends on VIDEO_VGA_VIA_LCD
677 Say Y here if you've a board which uses opendrain drivers for the vga
678 hsync and vsync signals. Opendrain drivers cannot generate steep enough
679 positive edges for a stable video output, so on boards with opendrain
680 drivers the sync signals must always be active high.
682 config VIDEO_VGA_EXTERNAL_DAC_EN
683 string "LCD panel power enable pin"
684 depends on VIDEO_VGA_VIA_LCD
687 Set the enable pin for the external VGA DAC. This takes a string in the
688 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
690 config VIDEO_COMPOSITE
691 bool "Composite video output support"
692 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
695 Say Y here to add support for outputting composite video.
697 config VIDEO_LCD_MODE
698 string "LCD panel timing details"
699 depends on VIDEO_SUNXI
702 LCD panel timing details string, leave empty if there is no LCD panel.
703 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
704 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
705 Also see: http://linux-sunxi.org/LCD
707 config VIDEO_LCD_DCLK_PHASE
708 int "LCD panel display clock phase"
709 depends on VIDEO_SUNXI || DM_VIDEO
712 Select LCD panel display clock phase shift, range 0-3.
714 config VIDEO_LCD_POWER
715 string "LCD panel power enable pin"
716 depends on VIDEO_SUNXI
719 Set the power enable pin for the LCD panel. This takes a string in the
720 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
722 config VIDEO_LCD_RESET
723 string "LCD panel reset pin"
724 depends on VIDEO_SUNXI
727 Set the reset pin for the LCD panel. This takes a string in the format
728 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
730 config VIDEO_LCD_BL_EN
731 string "LCD panel backlight enable pin"
732 depends on VIDEO_SUNXI
735 Set the backlight enable pin for the LCD panel. This takes a string in the
736 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
739 config VIDEO_LCD_BL_PWM
740 string "LCD panel backlight pwm pin"
741 depends on VIDEO_SUNXI
744 Set the backlight pwm pin for the LCD panel. This takes a string in the
745 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
747 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
748 bool "LCD panel backlight pwm is inverted"
749 depends on VIDEO_SUNXI
752 Set this if the backlight pwm output is active low.
754 config VIDEO_LCD_PANEL_I2C
755 bool "LCD panel needs to be configured via i2c"
756 depends on VIDEO_SUNXI
760 Say y here if the LCD panel needs to be configured via i2c. This
761 will add a bitbang i2c controller using gpios to talk to the LCD.
763 config VIDEO_LCD_PANEL_I2C_SDA
764 string "LCD panel i2c interface SDA pin"
765 depends on VIDEO_LCD_PANEL_I2C
768 Set the SDA pin for the LCD i2c interface. This takes a string in the
769 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
771 config VIDEO_LCD_PANEL_I2C_SCL
772 string "LCD panel i2c interface SCL pin"
773 depends on VIDEO_LCD_PANEL_I2C
776 Set the SCL pin for the LCD i2c interface. This takes a string in the
777 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
780 # Note only one of these may be selected at a time! But hidden choices are
781 # not supported by Kconfig
782 config VIDEO_LCD_IF_PARALLEL
785 config VIDEO_LCD_IF_LVDS
793 bool "Display Engine 2 video driver"
797 imply VIDEO_DT_SIMPLEFB
800 Say y here if you want to build DE2 video driver which is present on
801 newer SoCs. Currently only HDMI output is supported.
805 prompt "LCD panel support"
806 depends on VIDEO_SUNXI
808 Select which type of LCD panel to support.
810 config VIDEO_LCD_PANEL_PARALLEL
811 bool "Generic parallel interface LCD panel"
812 select VIDEO_LCD_IF_PARALLEL
814 config VIDEO_LCD_PANEL_LVDS
815 bool "Generic lvds interface LCD panel"
816 select VIDEO_LCD_IF_LVDS
818 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
819 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
820 select VIDEO_LCD_SSD2828
821 select VIDEO_LCD_IF_PARALLEL
823 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
825 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
826 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
827 select VIDEO_LCD_ANX9804
828 select VIDEO_LCD_IF_PARALLEL
829 select VIDEO_LCD_PANEL_I2C
831 Select this for eDP LCD panels with 4 lanes running at 1.62G,
832 connected via an ANX9804 bridge chip.
834 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
835 bool "Hitachi tx18d42vm LCD panel"
836 select VIDEO_LCD_HITACHI_TX18D42VM
837 select VIDEO_LCD_IF_LVDS
839 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
841 config VIDEO_LCD_TL059WV5C0
842 bool "tl059wv5c0 LCD panel"
843 select VIDEO_LCD_PANEL_I2C
844 select VIDEO_LCD_IF_PARALLEL
846 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
847 Aigo M60/M608/M606 tablets.
852 string "SATA power pin"
855 Set the pins used to power the SATA. This takes a string in the
856 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
860 int "GMAC Transmit Clock Delay Chain"
863 Set the GMAC Transmit Clock Delay Chain value.
865 config SPL_STACK_R_ADDR
866 default 0x4fe00000 if MACH_SUN4I
867 default 0x4fe00000 if MACH_SUN5I
868 default 0x4fe00000 if MACH_SUN6I
869 default 0x4fe00000 if MACH_SUN7I
870 default 0x4fe00000 if MACH_SUN8I
871 default 0x2fe00000 if MACH_SUN9I
872 default 0x4fe00000 if MACH_SUN50I
875 bool "Support for SPI Flash on Allwinner SoCs in SPL"
876 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
878 Enable support for SPI Flash. This option allows SPL to read from
879 sunxi SPI Flash. It uses the same method as the boot ROM, so does
880 not need any extra configuration.