4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
154 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
157 bool "sun9i (Allwinner A80)"
159 select SUNXI_HIGH_SRAM
160 select SUNXI_GEN_SUN6I
164 bool "sun50i (Allwinner A64)"
168 select SUNXI_GEN_SUN6I
169 select SUNXI_HIGH_SRAM
172 select SUNXI_DRAM_DW_32BIT
176 config MACH_SUN50I_H5
177 bool "sun50i (Allwinner H5)"
179 select MACH_SUNXI_H3_H5
180 select SUNXI_HIGH_SRAM
186 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
189 default y if MACH_SUN8I_A23
190 default y if MACH_SUN8I_A33
191 default y if MACH_SUN8I_A83T
192 default y if MACH_SUNXI_H3_H5
193 default y if MACH_SUN8I_R40
194 default y if MACH_SUN8I_V3S
196 config RESERVE_ALLWINNER_BOOT0_HEADER
197 bool "reserve space for Allwinner boot0 header"
198 select ENABLE_ARM_SOC_BOOT0_HOOK
200 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
201 filled with magic values post build. The Allwinner provided boot0
202 blob relies on this information to load and execute U-Boot.
203 Only needed on 64-bit Allwinner boards so far when using boot0.
205 config ARM_BOOT_HOOK_RMR
209 select ENABLE_ARM_SOC_BOOT0_HOOK
211 Insert some ARM32 code at the very beginning of the U-Boot binary
212 which uses an RMR register write to bring the core into AArch64 mode.
213 The very first instruction acts as a switch, since it's carefully
214 chosen to be a NOP in one mode and a branch in the other, so the
215 code would only be executed if not already in AArch64.
216 This allows both the SPL and the U-Boot proper to be entered in
217 either mode and switch to AArch64 if needed.
220 int "sunxi dram type"
221 depends on MACH_SUN8I_A83T
224 Set the dram type, 3: DDR3, 7: LPDDR3
227 int "sunxi dram clock speed"
228 default 792 if MACH_SUN9I
229 default 648 if MACH_SUN8I_R40
230 default 312 if MACH_SUN6I || MACH_SUN8I
231 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
232 default 672 if MACH_SUN50I
234 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
235 must be a multiple of 24. For the sun9i (A80), the tested values
236 (for DDR3-1600) are 312 to 792.
238 if MACH_SUN5I || MACH_SUN7I
240 int "sunxi mbus clock speed"
243 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
248 int "sunxi dram zq value"
249 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
250 default 127 if MACH_SUN7I
251 default 3881979 if MACH_SUN8I_R40
252 default 4145117 if MACH_SUN9I
253 default 3881915 if MACH_SUN50I
255 Set the dram zq value.
258 bool "sunxi dram odt enable"
259 default n if !MACH_SUN8I_A23
260 default y if MACH_SUN8I_A23
261 default y if MACH_SUN8I_R40
262 default y if MACH_SUN50I
264 Select this to enable dram odt (on die termination).
266 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
268 int "sunxi dram emr1 value"
269 default 0 if MACH_SUN4I
270 default 4 if MACH_SUN5I || MACH_SUN7I
272 Set the dram controller emr1 value.
275 hex "sunxi dram tpr3 value"
278 Set the dram controller tpr3 parameter. This parameter configures
279 the delay on the command lane and also phase shifts, which are
280 applied for sampling incoming read data. The default value 0
281 means that no phase/delay adjustments are necessary. Properly
282 configuring this parameter increases reliability at high DRAM
285 config DRAM_DQS_GATING_DELAY
286 hex "sunxi dram dqs_gating_delay value"
289 Set the dram controller dqs_gating_delay parmeter. Each byte
290 encodes the DQS gating delay for each byte lane. The delay
291 granularity is 1/4 cycle. For example, the value 0x05060606
292 means that the delay is 5 quarter-cycles for one lane (1.25
293 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
294 The default value 0 means autodetection. The results of hardware
295 autodetection are not very reliable and depend on the chip
296 temperature (sometimes producing different results on cold start
297 and warm reboot). But the accuracy of hardware autodetection
298 is usually good enough, unless running at really high DRAM
299 clocks speeds (up to 600MHz). If unsure, keep as 0.
302 prompt "sunxi dram timings"
303 default DRAM_TIMINGS_VENDOR_MAGIC
305 Select the timings of the DDR3 chips.
307 config DRAM_TIMINGS_VENDOR_MAGIC
308 bool "Magic vendor timings from Android"
310 The same DRAM timings as in the Allwinner boot0 bootloader.
312 config DRAM_TIMINGS_DDR3_1066F_1333H
313 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
315 Use the timings of the standard JEDEC DDR3-1066F speed bin for
316 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
317 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
318 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
319 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
320 that down binning to DDR3-1066F is supported (because DDR3-1066F
321 uses a bit faster timings than DDR3-1333H).
323 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
324 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
326 Use the timings of the slowest possible JEDEC speed bin for the
327 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
328 DDR3-800E, DDR3-1066G or DDR3-1333J.
335 config DRAM_ODT_CORRECTION
336 int "sunxi dram odt correction value"
339 Set the dram odt correction value (range -255 - 255). In allwinner
340 fex files, this option is found in bits 8-15 of the u32 odt_en variable
341 in the [dram] section. When bit 31 of the odt_en variable is set
342 then the correction is negative. Usually the value for this is 0.
346 default 1008000000 if MACH_SUN4I
347 default 1008000000 if MACH_SUN5I
348 default 1008000000 if MACH_SUN6I
349 default 912000000 if MACH_SUN7I
350 default 1008000000 if MACH_SUN8I
351 default 1008000000 if MACH_SUN9I
352 default 816000000 if MACH_SUN50I
354 config SYS_CONFIG_NAME
355 default "sun4i" if MACH_SUN4I
356 default "sun5i" if MACH_SUN5I
357 default "sun6i" if MACH_SUN6I
358 default "sun7i" if MACH_SUN7I
359 default "sun8i" if MACH_SUN8I
360 default "sun9i" if MACH_SUN9I
361 default "sun50i" if MACH_SUN50I
370 bool "UART0 on MicroSD breakout board"
373 Repurpose the SD card slot for getting access to the UART0 serial
374 console. Primarily useful only for low level u-boot debugging on
375 tablets, where normal UART0 is difficult to access and requires
376 device disassembly and/or soldering. As the SD card can't be used
377 at the same time, the system can be only booted in the FEL mode.
378 Only enable this if you really know what you are doing.
380 config OLD_SUNXI_KERNEL_COMPAT
381 bool "Enable workarounds for booting old kernels"
384 Set this to enable various workarounds for old kernels, this results in
385 sub-optimal settings for newer kernels, only enable if needed.
388 string "MAC power pin"
391 Set the pin used to power the MAC. This takes a string in the format
392 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
395 string "Card detect pin for mmc0"
396 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
399 Set the card detect pin for mmc0, leave empty to not use cd. This
400 takes a string in the format understood by sunxi_name_to_gpio, e.g.
401 PH1 for pin 1 of port H.
404 string "Card detect pin for mmc1"
407 See MMC0_CD_PIN help text.
410 string "Card detect pin for mmc2"
413 See MMC0_CD_PIN help text.
416 string "Card detect pin for mmc3"
419 See MMC0_CD_PIN help text.
422 string "Pins for mmc1"
425 Set the pins used for mmc1, when applicable. This takes a string in the
426 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
429 string "Pins for mmc2"
432 See MMC1_PINS help text.
435 string "Pins for mmc3"
438 See MMC1_PINS help text.
440 config MMC_SUNXI_SLOT_EXTRA
441 int "mmc extra slot number"
444 sunxi builds always enable mmc0, some boards also have a second sdcard
445 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
448 config INITIAL_USB_SCAN_DELAY
449 int "delay initial usb scan by x ms to allow builtin devices to init"
452 Some boards have on board usb devices which need longer than the
453 USB spec's 1 second to connect from board powerup. Set this config
454 option to a non 0 value to add an extra delay before the first usb
458 string "Vbus enable pin for usb0 (otg)"
461 Set the Vbus enable pin for usb0 (otg). This takes a string in the
462 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
465 string "Vbus detect pin for usb0 (otg)"
468 Set the Vbus detect pin for usb0 (otg). This takes a string in the
469 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
472 string "ID detect pin for usb0 (otg)"
475 Set the ID detect pin for usb0 (otg). This takes a string in the
476 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
479 string "Vbus enable pin for usb1 (ehci0)"
480 default "PH6" if MACH_SUN4I || MACH_SUN7I
481 default "PH27" if MACH_SUN6I
483 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
484 a string in the format understood by sunxi_name_to_gpio, e.g.
485 PH1 for pin 1 of port H.
488 string "Vbus enable pin for usb2 (ehci1)"
489 default "PH3" if MACH_SUN4I || MACH_SUN7I
490 default "PH24" if MACH_SUN6I
492 See USB1_VBUS_PIN help text.
495 string "Vbus enable pin for usb3 (ehci2)"
498 See USB1_VBUS_PIN help text.
501 bool "Enable I2C/TWI controller 0"
502 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
503 default n if MACH_SUN6I || MACH_SUN8I
506 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
507 its clock and setting up the bus. This is especially useful on devices
508 with slaves connected to the bus or with pins exposed through e.g. an
509 expansion port/header.
512 bool "Enable I2C/TWI controller 1"
516 See I2C0_ENABLE help text.
519 bool "Enable I2C/TWI controller 2"
523 See I2C0_ENABLE help text.
525 if MACH_SUN6I || MACH_SUN7I
527 bool "Enable I2C/TWI controller 3"
531 See I2C0_ENABLE help text.
536 bool "Enable the PRCM I2C/TWI controller"
537 # This is used for the pmic on H3
538 default y if SY8106A_POWER
541 Set this to y to enable the I2C controller which is part of the PRCM.
546 bool "Enable I2C/TWI controller 4"
550 See I2C0_ENABLE help text.
554 bool "Enable support for gpio-s on axp PMICs"
557 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
560 bool "Enable graphical uboot console on HDMI, LCD or VGA"
561 depends on !MACH_SUN8I_A83T
562 depends on !MACH_SUNXI_H3_H5
563 depends on !MACH_SUN8I_R40
564 depends on !MACH_SUN8I_V3S
565 depends on !MACH_SUN9I
566 depends on !MACH_SUN50I
569 Say Y here to add support for using a cfb console on the HDMI, LCD
570 or VGA output found on most sunxi devices. See doc/README.video for
571 info on how to select the video output and mode.
574 bool "HDMI output support"
575 depends on VIDEO && !MACH_SUN8I
578 Say Y here to add support for outputting video over HDMI.
581 bool "VGA output support"
582 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
585 Say Y here to add support for outputting video over VGA.
587 config VIDEO_VGA_VIA_LCD
588 bool "VGA via LCD controller support"
589 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
592 Say Y here to add support for external DACs connected to the parallel
593 LCD interface driving a VGA connector, such as found on the
596 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
597 bool "Force sync active high for VGA via LCD controller support"
598 depends on VIDEO_VGA_VIA_LCD
601 Say Y here if you've a board which uses opendrain drivers for the vga
602 hsync and vsync signals. Opendrain drivers cannot generate steep enough
603 positive edges for a stable video output, so on boards with opendrain
604 drivers the sync signals must always be active high.
606 config VIDEO_VGA_EXTERNAL_DAC_EN
607 string "LCD panel power enable pin"
608 depends on VIDEO_VGA_VIA_LCD
611 Set the enable pin for the external VGA DAC. This takes a string in the
612 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
614 config VIDEO_COMPOSITE
615 bool "Composite video output support"
616 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
619 Say Y here to add support for outputting composite video.
621 config VIDEO_LCD_MODE
622 string "LCD panel timing details"
626 LCD panel timing details string, leave empty if there is no LCD panel.
627 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
628 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
629 Also see: http://linux-sunxi.org/LCD
631 config VIDEO_LCD_DCLK_PHASE
632 int "LCD panel display clock phase"
636 Select LCD panel display clock phase shift, range 0-3.
638 config VIDEO_LCD_POWER
639 string "LCD panel power enable pin"
643 Set the power enable pin for the LCD panel. This takes a string in the
644 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
646 config VIDEO_LCD_RESET
647 string "LCD panel reset pin"
651 Set the reset pin for the LCD panel. This takes a string in the format
652 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
654 config VIDEO_LCD_BL_EN
655 string "LCD panel backlight enable pin"
659 Set the backlight enable pin for the LCD panel. This takes a string in the
660 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
663 config VIDEO_LCD_BL_PWM
664 string "LCD panel backlight pwm pin"
668 Set the backlight pwm pin for the LCD panel. This takes a string in the
669 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
671 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
672 bool "LCD panel backlight pwm is inverted"
676 Set this if the backlight pwm output is active low.
678 config VIDEO_LCD_PANEL_I2C
679 bool "LCD panel needs to be configured via i2c"
684 Say y here if the LCD panel needs to be configured via i2c. This
685 will add a bitbang i2c controller using gpios to talk to the LCD.
687 config VIDEO_LCD_PANEL_I2C_SDA
688 string "LCD panel i2c interface SDA pin"
689 depends on VIDEO_LCD_PANEL_I2C
692 Set the SDA pin for the LCD i2c interface. This takes a string in the
693 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
695 config VIDEO_LCD_PANEL_I2C_SCL
696 string "LCD panel i2c interface SCL pin"
697 depends on VIDEO_LCD_PANEL_I2C
700 Set the SCL pin for the LCD i2c interface. This takes a string in the
701 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
704 # Note only one of these may be selected at a time! But hidden choices are
705 # not supported by Kconfig
706 config VIDEO_LCD_IF_PARALLEL
709 config VIDEO_LCD_IF_LVDS
717 bool "Display Engine 2 video driver"
723 Say y here if you want to build DE2 video driver which is present on
724 newer SoCs. Currently only HDMI output is supported.
728 prompt "LCD panel support"
731 Select which type of LCD panel to support.
733 config VIDEO_LCD_PANEL_PARALLEL
734 bool "Generic parallel interface LCD panel"
735 select VIDEO_LCD_IF_PARALLEL
737 config VIDEO_LCD_PANEL_LVDS
738 bool "Generic lvds interface LCD panel"
739 select VIDEO_LCD_IF_LVDS
741 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
742 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
743 select VIDEO_LCD_SSD2828
744 select VIDEO_LCD_IF_PARALLEL
746 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
748 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
749 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
750 select VIDEO_LCD_ANX9804
751 select VIDEO_LCD_IF_PARALLEL
752 select VIDEO_LCD_PANEL_I2C
754 Select this for eDP LCD panels with 4 lanes running at 1.62G,
755 connected via an ANX9804 bridge chip.
757 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
758 bool "Hitachi tx18d42vm LCD panel"
759 select VIDEO_LCD_HITACHI_TX18D42VM
760 select VIDEO_LCD_IF_LVDS
762 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
764 config VIDEO_LCD_TL059WV5C0
765 bool "tl059wv5c0 LCD panel"
766 select VIDEO_LCD_PANEL_I2C
767 select VIDEO_LCD_IF_PARALLEL
769 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
770 Aigo M60/M608/M606 tablets.
775 string "SATA power pin"
778 Set the pins used to power the SATA. This takes a string in the
779 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
783 int "GMAC Transmit Clock Delay Chain"
786 Set the GMAC Transmit Clock Delay Chain value.
788 config SPL_STACK_R_ADDR
789 default 0x4fe00000 if MACH_SUN4I
790 default 0x4fe00000 if MACH_SUN5I
791 default 0x4fe00000 if MACH_SUN6I
792 default 0x4fe00000 if MACH_SUN7I
793 default 0x4fe00000 if MACH_SUN8I
794 default 0x2fe00000 if MACH_SUN9I
795 default 0x4fe00000 if MACH_SUN50I