4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
46 bool "Allwinner sun6i internal P2WI controller"
48 If you say yes to this option, support will be included for the
49 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
51 The P2WI looks like an SMBus controller (which supports only byte
52 accesses), except that it only supports one slave device.
53 This interface is used to connect to specific PMIC devices (like the
59 Support for the PRCM (Power/Reset/Clock Management) unit available
63 bool "Sunxi AXP PMIC bus access helpers"
65 Select this PMIC bus access helpers for Sunxi platform PRCM or other
66 AXP family PMIC devices.
69 bool "Allwinner sunXi Reduced Serial Bus Driver"
71 Say y here to enable support for Allwinner's Reduced Serial Bus
72 (RSB) support. This controller is responsible for communicating
73 with various RSB based devices, such as AXP223, AXP8XX PMICs,
76 config SUNXI_HIGH_SRAM
80 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
81 with the first SRAM region being located at address 0.
82 Some newer SoCs map the boot ROM at address 0 instead and move the
83 SRAM to 64KB, just behind the mask ROM.
84 Chips using the latter setup are supposed to select this option to
85 adjust the addresses accordingly.
87 config SUNXI_A64_TIMER_ERRATUM
90 # Note only one of these may be selected at a time! But hidden choices are
91 # not supported by Kconfig
92 config SUNXI_GEN_SUN4I
95 Select this for sunxi SoCs which have resets and clocks set up
96 as the original A10 (mach-sun4i).
98 config SUNXI_GEN_SUN6I
101 Select this for sunxi SoCs which have sun6i like periphery, like
102 separate ahb reset control registers, custom pmic bus, new style
108 Select this for sunxi SoCs which uses a DRAM controller like the
109 DesignWare controller used in H3, mainly SoCs after H3, which do
110 not have official open-source DRAM initialization code, but can
111 use modified H3 DRAM initialization code.
114 config SUNXI_DRAM_DW_16BIT
117 Select this for sunxi SoCs with DesignWare DRAM controller and
118 have only 16-bit memory buswidth.
120 config SUNXI_DRAM_DW_32BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller with
124 32-bit memory buswidth.
127 config MACH_SUNXI_H3_H5
133 select SUNXI_DRAM_DW_32BIT
134 select SUNXI_GEN_SUN6I
138 prompt "Sunxi SoC Variant"
142 bool "sun4i (Allwinner A10)"
144 select ARM_CORTEX_CPU_IS_UP
146 select DM_SCSI if SCSI
149 select SUNXI_GEN_SUN4I
153 bool "sun5i (Allwinner A13)"
155 select ARM_CORTEX_CPU_IS_UP
158 select SUNXI_GEN_SUN4I
160 imply CONS_INDEX_2 if !DM_SERIAL
163 bool "sun6i (Allwinner A31)"
165 select CPU_V7_HAS_NONSEC
166 select CPU_V7_HAS_VIRT
167 select ARCH_SUPPORT_PSCI
172 select SUNXI_GEN_SUN6I
174 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
177 bool "sun7i (Allwinner A20)"
179 select CPU_V7_HAS_NONSEC
180 select CPU_V7_HAS_VIRT
181 select ARCH_SUPPORT_PSCI
184 select SUNXI_GEN_SUN4I
186 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
188 config MACH_SUN8I_A23
189 bool "sun8i (Allwinner A23)"
191 select CPU_V7_HAS_NONSEC
192 select CPU_V7_HAS_VIRT
193 select ARCH_SUPPORT_PSCI
194 select DRAM_SUN8I_A23
196 select SUNXI_GEN_SUN6I
198 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
199 imply CONS_INDEX_5 if !DM_SERIAL
201 config MACH_SUN8I_A33
202 bool "sun8i (Allwinner A33)"
204 select CPU_V7_HAS_NONSEC
205 select CPU_V7_HAS_VIRT
206 select ARCH_SUPPORT_PSCI
207 select DRAM_SUN8I_A33
209 select SUNXI_GEN_SUN6I
211 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
212 imply CONS_INDEX_5 if !DM_SERIAL
214 config MACH_SUN8I_A83T
215 bool "sun8i (Allwinner A83T)"
217 select DRAM_SUN8I_A83T
219 select SUNXI_GEN_SUN6I
220 select MMC_SUNXI_HAS_NEW_MODE
224 bool "sun8i (Allwinner H3)"
226 select CPU_V7_HAS_NONSEC
227 select CPU_V7_HAS_VIRT
228 select ARCH_SUPPORT_PSCI
229 select MACH_SUNXI_H3_H5
230 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
232 config MACH_SUN8I_R40
233 bool "sun8i (Allwinner R40)"
235 select CPU_V7_HAS_NONSEC
236 select CPU_V7_HAS_VIRT
237 select ARCH_SUPPORT_PSCI
238 select SUNXI_GEN_SUN6I
241 select SUNXI_DRAM_DW_32BIT
243 config MACH_SUN8I_V3S
244 bool "sun8i (Allwinner V3s)"
246 select CPU_V7_HAS_NONSEC
247 select CPU_V7_HAS_VIRT
248 select ARCH_SUPPORT_PSCI
249 select SUNXI_GEN_SUN6I
251 select SUNXI_DRAM_DW_16BIT
253 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
256 bool "sun9i (Allwinner A80)"
260 select SUNXI_HIGH_SRAM
261 select SUNXI_GEN_SUN6I
266 bool "sun50i (Allwinner A64)"
271 select SUNXI_GEN_SUN6I
272 select SUNXI_HIGH_SRAM
275 select SUNXI_DRAM_DW_32BIT
278 select SUNXI_A64_TIMER_ERRATUM
280 config MACH_SUN50I_H5
281 bool "sun50i (Allwinner H5)"
283 select MACH_SUNXI_H3_H5
284 select SUNXI_HIGH_SRAM
290 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
295 default y if MACH_SUN8I_A23
296 default y if MACH_SUN8I_A33
297 default y if MACH_SUN8I_A83T
298 default y if MACH_SUNXI_H3_H5
299 default y if MACH_SUN8I_R40
300 default y if MACH_SUN8I_V3S
302 config RESERVE_ALLWINNER_BOOT0_HEADER
303 bool "reserve space for Allwinner boot0 header"
304 select ENABLE_ARM_SOC_BOOT0_HOOK
306 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
307 filled with magic values post build. The Allwinner provided boot0
308 blob relies on this information to load and execute U-Boot.
309 Only needed on 64-bit Allwinner boards so far when using boot0.
311 config ARM_BOOT_HOOK_RMR
315 select ENABLE_ARM_SOC_BOOT0_HOOK
317 Insert some ARM32 code at the very beginning of the U-Boot binary
318 which uses an RMR register write to bring the core into AArch64 mode.
319 The very first instruction acts as a switch, since it's carefully
320 chosen to be a NOP in one mode and a branch in the other, so the
321 code would only be executed if not already in AArch64.
322 This allows both the SPL and the U-Boot proper to be entered in
323 either mode and switch to AArch64 if needed.
326 config SUNXI_DRAM_DDR3
329 config SUNXI_DRAM_DDR2
332 config SUNXI_DRAM_LPDDR3
336 prompt "DRAM Type and Timing"
337 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
338 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
340 config SUNXI_DRAM_DDR3_1333
342 select SUNXI_DRAM_DDR3
343 depends on !MACH_SUN8I_V3S
345 This option is the original only supported memory type, which suits
346 many H3/H5/A64 boards available now.
348 config SUNXI_DRAM_LPDDR3_STOCK
349 bool "LPDDR3 with Allwinner stock configuration"
350 select SUNXI_DRAM_LPDDR3
352 This option is the LPDDR3 timing used by the stock boot0 by
355 config SUNXI_DRAM_DDR2_V3S
356 bool "DDR2 found in V3s chip"
357 select SUNXI_DRAM_DDR2
358 depends on MACH_SUN8I_V3S
360 This option is only for the DDR2 memory chip which is co-packaged in
367 int "sunxi dram type"
368 depends on MACH_SUN8I_A83T
371 Set the dram type, 3: DDR3, 7: LPDDR3
374 int "sunxi dram clock speed"
375 default 792 if MACH_SUN9I
376 default 648 if MACH_SUN8I_R40
377 default 312 if MACH_SUN6I || MACH_SUN8I
378 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
380 default 672 if MACH_SUN50I
382 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
383 must be a multiple of 24. For the sun9i (A80), the tested values
384 (for DDR3-1600) are 312 to 792.
386 if MACH_SUN5I || MACH_SUN7I
388 int "sunxi mbus clock speed"
391 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
396 int "sunxi dram zq value"
397 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
398 default 127 if MACH_SUN7I
399 default 14779 if MACH_SUN8I_V3S
400 default 3881979 if MACH_SUN8I_R40
401 default 4145117 if MACH_SUN9I
402 default 3881915 if MACH_SUN50I
404 Set the dram zq value.
407 bool "sunxi dram odt enable"
408 default n if !MACH_SUN8I_A23
409 default y if MACH_SUN8I_A23
410 default y if MACH_SUN8I_R40
411 default y if MACH_SUN50I
413 Select this to enable dram odt (on die termination).
415 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
417 int "sunxi dram emr1 value"
418 default 0 if MACH_SUN4I
419 default 4 if MACH_SUN5I || MACH_SUN7I
421 Set the dram controller emr1 value.
424 hex "sunxi dram tpr3 value"
427 Set the dram controller tpr3 parameter. This parameter configures
428 the delay on the command lane and also phase shifts, which are
429 applied for sampling incoming read data. The default value 0
430 means that no phase/delay adjustments are necessary. Properly
431 configuring this parameter increases reliability at high DRAM
434 config DRAM_DQS_GATING_DELAY
435 hex "sunxi dram dqs_gating_delay value"
438 Set the dram controller dqs_gating_delay parmeter. Each byte
439 encodes the DQS gating delay for each byte lane. The delay
440 granularity is 1/4 cycle. For example, the value 0x05060606
441 means that the delay is 5 quarter-cycles for one lane (1.25
442 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
443 The default value 0 means autodetection. The results of hardware
444 autodetection are not very reliable and depend on the chip
445 temperature (sometimes producing different results on cold start
446 and warm reboot). But the accuracy of hardware autodetection
447 is usually good enough, unless running at really high DRAM
448 clocks speeds (up to 600MHz). If unsure, keep as 0.
451 prompt "sunxi dram timings"
452 default DRAM_TIMINGS_VENDOR_MAGIC
454 Select the timings of the DDR3 chips.
456 config DRAM_TIMINGS_VENDOR_MAGIC
457 bool "Magic vendor timings from Android"
459 The same DRAM timings as in the Allwinner boot0 bootloader.
461 config DRAM_TIMINGS_DDR3_1066F_1333H
462 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
464 Use the timings of the standard JEDEC DDR3-1066F speed bin for
465 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
466 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
467 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
468 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
469 that down binning to DDR3-1066F is supported (because DDR3-1066F
470 uses a bit faster timings than DDR3-1333H).
472 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
473 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
475 Use the timings of the slowest possible JEDEC speed bin for the
476 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
477 DDR3-800E, DDR3-1066G or DDR3-1333J.
484 config DRAM_ODT_CORRECTION
485 int "sunxi dram odt correction value"
488 Set the dram odt correction value (range -255 - 255). In allwinner
489 fex files, this option is found in bits 8-15 of the u32 odt_en variable
490 in the [dram] section. When bit 31 of the odt_en variable is set
491 then the correction is negative. Usually the value for this is 0.
495 default 1008000000 if MACH_SUN4I
496 default 1008000000 if MACH_SUN5I
497 default 1008000000 if MACH_SUN6I
498 default 912000000 if MACH_SUN7I
499 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
500 default 1008000000 if MACH_SUN8I
501 default 1008000000 if MACH_SUN9I
503 config SYS_CONFIG_NAME
504 default "sun4i" if MACH_SUN4I
505 default "sun5i" if MACH_SUN5I
506 default "sun6i" if MACH_SUN6I
507 default "sun7i" if MACH_SUN7I
508 default "sun8i" if MACH_SUN8I
509 default "sun9i" if MACH_SUN9I
510 default "sun50i" if MACH_SUN50I
519 bool "UART0 on MicroSD breakout board"
522 Repurpose the SD card slot for getting access to the UART0 serial
523 console. Primarily useful only for low level u-boot debugging on
524 tablets, where normal UART0 is difficult to access and requires
525 device disassembly and/or soldering. As the SD card can't be used
526 at the same time, the system can be only booted in the FEL mode.
527 Only enable this if you really know what you are doing.
529 config OLD_SUNXI_KERNEL_COMPAT
530 bool "Enable workarounds for booting old kernels"
533 Set this to enable various workarounds for old kernels, this results in
534 sub-optimal settings for newer kernels, only enable if needed.
537 string "MAC power pin"
540 Set the pin used to power the MAC. This takes a string in the format
541 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
544 string "Card detect pin for mmc0"
545 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
548 Set the card detect pin for mmc0, leave empty to not use cd. This
549 takes a string in the format understood by sunxi_name_to_gpio, e.g.
550 PH1 for pin 1 of port H.
553 string "Card detect pin for mmc1"
556 See MMC0_CD_PIN help text.
559 string "Card detect pin for mmc2"
562 See MMC0_CD_PIN help text.
565 string "Card detect pin for mmc3"
568 See MMC0_CD_PIN help text.
571 string "Pins for mmc1"
574 Set the pins used for mmc1, when applicable. This takes a string in the
575 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
578 string "Pins for mmc2"
581 See MMC1_PINS help text.
584 string "Pins for mmc3"
587 See MMC1_PINS help text.
589 config MMC_SUNXI_SLOT_EXTRA
590 int "mmc extra slot number"
593 sunxi builds always enable mmc0, some boards also have a second sdcard
594 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
597 config INITIAL_USB_SCAN_DELAY
598 int "delay initial usb scan by x ms to allow builtin devices to init"
601 Some boards have on board usb devices which need longer than the
602 USB spec's 1 second to connect from board powerup. Set this config
603 option to a non 0 value to add an extra delay before the first usb
607 string "Vbus enable pin for usb0 (otg)"
610 Set the Vbus enable pin for usb0 (otg). This takes a string in the
611 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
614 string "Vbus detect pin for usb0 (otg)"
617 Set the Vbus detect pin for usb0 (otg). This takes a string in the
618 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
621 string "ID detect pin for usb0 (otg)"
624 Set the ID detect pin for usb0 (otg). This takes a string in the
625 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
628 string "Vbus enable pin for usb1 (ehci0)"
629 default "PH6" if MACH_SUN4I || MACH_SUN7I
630 default "PH27" if MACH_SUN6I
632 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
633 a string in the format understood by sunxi_name_to_gpio, e.g.
634 PH1 for pin 1 of port H.
637 string "Vbus enable pin for usb2 (ehci1)"
638 default "PH3" if MACH_SUN4I || MACH_SUN7I
639 default "PH24" if MACH_SUN6I
641 See USB1_VBUS_PIN help text.
644 string "Vbus enable pin for usb3 (ehci2)"
647 See USB1_VBUS_PIN help text.
650 bool "Enable I2C/TWI controller 0"
651 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
652 default n if MACH_SUN6I || MACH_SUN8I
655 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
656 its clock and setting up the bus. This is especially useful on devices
657 with slaves connected to the bus or with pins exposed through e.g. an
658 expansion port/header.
661 bool "Enable I2C/TWI controller 1"
665 See I2C0_ENABLE help text.
668 bool "Enable I2C/TWI controller 2"
672 See I2C0_ENABLE help text.
674 if MACH_SUN6I || MACH_SUN7I
676 bool "Enable I2C/TWI controller 3"
680 See I2C0_ENABLE help text.
685 bool "Enable the PRCM I2C/TWI controller"
686 # This is used for the pmic on H3
687 default y if SY8106A_POWER
690 Set this to y to enable the I2C controller which is part of the PRCM.
695 bool "Enable I2C/TWI controller 4"
699 See I2C0_ENABLE help text.
703 bool "Enable support for gpio-s on axp PMICs"
706 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
709 bool "Enable graphical uboot console on HDMI, LCD or VGA"
710 depends on !MACH_SUN8I_A83T
711 depends on !MACH_SUNXI_H3_H5
712 depends on !MACH_SUN8I_R40
713 depends on !MACH_SUN8I_V3S
714 depends on !MACH_SUN9I
715 depends on !MACH_SUN50I
717 imply VIDEO_DT_SIMPLEFB
720 Say Y here to add support for using a cfb console on the HDMI, LCD
721 or VGA output found on most sunxi devices. See doc/README.video for
722 info on how to select the video output and mode.
725 bool "HDMI output support"
726 depends on VIDEO_SUNXI && !MACH_SUN8I
729 Say Y here to add support for outputting video over HDMI.
732 bool "VGA output support"
733 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
736 Say Y here to add support for outputting video over VGA.
738 config VIDEO_VGA_VIA_LCD
739 bool "VGA via LCD controller support"
740 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
743 Say Y here to add support for external DACs connected to the parallel
744 LCD interface driving a VGA connector, such as found on the
747 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
748 bool "Force sync active high for VGA via LCD controller support"
749 depends on VIDEO_VGA_VIA_LCD
752 Say Y here if you've a board which uses opendrain drivers for the vga
753 hsync and vsync signals. Opendrain drivers cannot generate steep enough
754 positive edges for a stable video output, so on boards with opendrain
755 drivers the sync signals must always be active high.
757 config VIDEO_VGA_EXTERNAL_DAC_EN
758 string "LCD panel power enable pin"
759 depends on VIDEO_VGA_VIA_LCD
762 Set the enable pin for the external VGA DAC. This takes a string in the
763 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
765 config VIDEO_COMPOSITE
766 bool "Composite video output support"
767 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
770 Say Y here to add support for outputting composite video.
772 config VIDEO_LCD_MODE
773 string "LCD panel timing details"
774 depends on VIDEO_SUNXI
777 LCD panel timing details string, leave empty if there is no LCD panel.
778 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
779 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
780 Also see: http://linux-sunxi.org/LCD
782 config VIDEO_LCD_DCLK_PHASE
783 int "LCD panel display clock phase"
784 depends on VIDEO_SUNXI || DM_VIDEO
787 Select LCD panel display clock phase shift, range 0-3.
789 config VIDEO_LCD_POWER
790 string "LCD panel power enable pin"
791 depends on VIDEO_SUNXI
794 Set the power enable pin for the LCD panel. This takes a string in the
795 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
797 config VIDEO_LCD_RESET
798 string "LCD panel reset pin"
799 depends on VIDEO_SUNXI
802 Set the reset pin for the LCD panel. This takes a string in the format
803 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
805 config VIDEO_LCD_BL_EN
806 string "LCD panel backlight enable pin"
807 depends on VIDEO_SUNXI
810 Set the backlight enable pin for the LCD panel. This takes a string in the
811 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
814 config VIDEO_LCD_BL_PWM
815 string "LCD panel backlight pwm pin"
816 depends on VIDEO_SUNXI
819 Set the backlight pwm pin for the LCD panel. This takes a string in the
820 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
822 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
823 bool "LCD panel backlight pwm is inverted"
824 depends on VIDEO_SUNXI
827 Set this if the backlight pwm output is active low.
829 config VIDEO_LCD_PANEL_I2C
830 bool "LCD panel needs to be configured via i2c"
831 depends on VIDEO_SUNXI
835 Say y here if the LCD panel needs to be configured via i2c. This
836 will add a bitbang i2c controller using gpios to talk to the LCD.
838 config VIDEO_LCD_PANEL_I2C_SDA
839 string "LCD panel i2c interface SDA pin"
840 depends on VIDEO_LCD_PANEL_I2C
843 Set the SDA pin for the LCD i2c interface. This takes a string in the
844 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
846 config VIDEO_LCD_PANEL_I2C_SCL
847 string "LCD panel i2c interface SCL pin"
848 depends on VIDEO_LCD_PANEL_I2C
851 Set the SCL pin for the LCD i2c interface. This takes a string in the
852 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
855 # Note only one of these may be selected at a time! But hidden choices are
856 # not supported by Kconfig
857 config VIDEO_LCD_IF_PARALLEL
860 config VIDEO_LCD_IF_LVDS
868 bool "Display Engine 2 video driver"
872 imply VIDEO_DT_SIMPLEFB
875 Say y here if you want to build DE2 video driver which is present on
876 newer SoCs. Currently only HDMI output is supported.
880 prompt "LCD panel support"
881 depends on VIDEO_SUNXI
883 Select which type of LCD panel to support.
885 config VIDEO_LCD_PANEL_PARALLEL
886 bool "Generic parallel interface LCD panel"
887 select VIDEO_LCD_IF_PARALLEL
889 config VIDEO_LCD_PANEL_LVDS
890 bool "Generic lvds interface LCD panel"
891 select VIDEO_LCD_IF_LVDS
893 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
894 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
895 select VIDEO_LCD_SSD2828
896 select VIDEO_LCD_IF_PARALLEL
898 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
900 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
901 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
902 select VIDEO_LCD_ANX9804
903 select VIDEO_LCD_IF_PARALLEL
904 select VIDEO_LCD_PANEL_I2C
906 Select this for eDP LCD panels with 4 lanes running at 1.62G,
907 connected via an ANX9804 bridge chip.
909 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
910 bool "Hitachi tx18d42vm LCD panel"
911 select VIDEO_LCD_HITACHI_TX18D42VM
912 select VIDEO_LCD_IF_LVDS
914 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
916 config VIDEO_LCD_TL059WV5C0
917 bool "tl059wv5c0 LCD panel"
918 select VIDEO_LCD_PANEL_I2C
919 select VIDEO_LCD_IF_PARALLEL
921 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
922 Aigo M60/M608/M606 tablets.
927 string "SATA power pin"
930 Set the pins used to power the SATA. This takes a string in the
931 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
935 int "GMAC Transmit Clock Delay Chain"
938 Set the GMAC Transmit Clock Delay Chain value.
940 config SPL_STACK_R_ADDR
941 default 0x4fe00000 if MACH_SUN4I
942 default 0x4fe00000 if MACH_SUN5I
943 default 0x4fe00000 if MACH_SUN6I
944 default 0x4fe00000 if MACH_SUN7I
945 default 0x4fe00000 if MACH_SUN8I
946 default 0x2fe00000 if MACH_SUN9I
947 default 0x4fe00000 if MACH_SUN50I
950 bool "Support for SPI Flash on Allwinner SoCs in SPL"
951 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
953 Enable support for SPI Flash. This option allows SPL to read from
954 sunxi SPI Flash. It uses the same method as the boot ROM, so does
955 not need any extra configuration.