2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
30 #include <linux/compiler.h>
41 struct fel_stash fel_stash __attribute__((section(".data")));
43 #ifdef CONFIG_MACH_SUN50I
44 #include <asm/armv8/mmu.h>
46 static struct mm_region sunxi_mem_map[] = {
48 /* SRAM, MMIO regions */
52 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
59 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
66 struct mm_region *mem_map = sunxi_mem_map;
69 static int gpio_init(void)
71 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
72 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
73 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
74 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
75 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
77 #if defined(CONFIG_MACH_SUN8I)
78 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
81 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
82 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
84 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
85 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
86 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
87 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
88 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
89 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
92 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
93 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
96 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
97 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
98 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
100 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
101 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
102 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
103 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
104 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
105 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
106 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
107 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
108 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
109 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
110 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
111 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
112 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
113 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
114 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
115 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
116 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
117 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
118 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
119 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
120 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
121 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
122 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
123 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
124 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
125 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
126 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
127 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
128 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
130 #error Unsupported console port number. Please fix pin mux settings in board.c
136 int spl_board_load_image(void)
138 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
139 return_to_fel(fel_stash.sp, fel_stash.lr);
147 * Undocumented magic taken from boot0, without this DRAM
148 * access gets messed up (seems cache related).
149 * The boot0 sources describe this as: "config ema for cache sram"
151 #if defined CONFIG_MACH_SUN6I
152 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
153 #elif defined CONFIG_MACH_SUN8I
154 __maybe_unused uint version;
156 /* Unlock sram version info reg, read it, relock */
157 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
158 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
159 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
162 * Ideally this would be a switch case, but we do not know exactly
163 * which versions there are and which version needs which settings,
164 * so reproduce the per SoC code from the BSP.
166 #if defined CONFIG_MACH_SUN8I_A23
167 if (version == 0x1650)
168 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
170 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
171 #elif defined CONFIG_MACH_SUN8I_A33
172 if (version != 0x1667)
173 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
175 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
176 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
179 #if defined CONFIG_MACH_SUN6I || \
180 defined CONFIG_MACH_SUN7I || \
181 defined CONFIG_MACH_SUN8I
182 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
184 "mrc p15, 0, r0, c1, c0, 1\n"
185 "orr r0, r0, #1 << 6\n"
186 "mcr p15, 0, r0, c1, c0, 1\n");
188 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
189 /* Enable non-secure access to some peripherals */
200 #ifdef CONFIG_SPL_BUILD
201 DECLARE_GLOBAL_DATA_PTR;
203 /* The sunxi internal brom will try to loader external bootloader
204 * from mmc0, nand flash, mmc2.
206 u32 spl_boot_device(void)
211 * When booting from the SD card or NAND memory, the "eGON.BT0"
212 * signature is expected to be found in memory at the address 0x0004
213 * (see the "mksunxiboot" tool, which generates this header).
215 * When booting in the FEL mode over USB, this signature is patched in
216 * memory and replaced with something else by the 'fel' tool. This other
217 * signature is selected in such a way, that it can't be present in a
218 * valid bootable SD card image (because the BROM would refuse to
219 * execute the SPL in this case).
221 * This checks for the signature and if it is not found returns to
222 * the FEL code in the BROM to wait and receive the main u-boot
223 * binary over USB. If it is found, it determines where SPL was
226 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
227 return BOOT_DEVICE_BOARD;
229 boot_source = readb(SPL_ADDR + 0x28);
230 switch (boot_source) {
231 case SUNXI_BOOTED_FROM_MMC0:
232 return BOOT_DEVICE_MMC1;
233 case SUNXI_BOOTED_FROM_NAND:
234 return BOOT_DEVICE_NAND;
235 case SUNXI_BOOTED_FROM_MMC2:
236 return BOOT_DEVICE_MMC2;
237 case SUNXI_BOOTED_FROM_SPI:
238 return BOOT_DEVICE_SPI;
241 panic("Unknown boot source %d\n", boot_source);
242 return -1; /* Never reached */
246 * Properly announce BOOT_DEVICE_BOARD as "FEL".
247 * Overrides weak function from common/spl/spl.c
249 void spl_board_announce_boot_device(void)
254 /* No confirmation data available in SPL yet. Hardcode bootmode */
255 u32 spl_boot_mode(const u32 boot_device)
257 return MMCSD_MODE_RAW;
260 void board_init_f(ulong dummy)
263 preloader_console_init();
265 #ifdef CONFIG_SPL_I2C_SUPPORT
266 /* Needed early by sunxi_board_init if PMU is enabled */
267 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
273 void reset_cpu(ulong addr)
275 #ifdef CONFIG_SUNXI_GEN_SUN4I
276 static const struct sunxi_wdog *wdog =
277 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
279 /* Set the watchdog for its shortest interval (.5s) and wait */
280 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
281 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
284 /* sun5i sometimes gets stuck without this */
285 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
288 #ifdef CONFIG_SUNXI_GEN_SUN6I
289 static const struct sunxi_wdog *wdog =
290 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
292 /* Set the watchdog for its shortest interval (.5s) and wait */
293 writel(WDT_CFG_RESET, &wdog->cfg);
294 writel(WDT_MODE_EN, &wdog->mode);
295 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
300 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
301 void enable_caches(void)
303 /* Enable D-cache. I-cache is already enabled in start.S */