2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/spl.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
27 #include <asm/arch/tzpc.h>
28 #include <asm/arch/mmc.h>
30 #include <linux/compiler.h>
41 struct fel_stash fel_stash __attribute__((section(".data")));
43 #ifdef CONFIG_MACH_SUN50I
44 #include <asm/armv8/mmu.h>
46 static struct mm_region sunxi_mem_map[] = {
48 /* SRAM, MMIO regions */
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
64 struct mm_region *mem_map = sunxi_mem_map;
67 static int gpio_init(void)
69 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
70 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
71 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
72 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
73 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
75 #if defined(CONFIG_MACH_SUN8I)
76 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
77 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
79 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
80 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
82 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
83 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
84 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
85 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
86 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
87 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
88 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
89 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
90 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
91 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
92 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
93 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
94 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
95 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
96 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
97 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
98 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
99 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
100 sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
102 sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
103 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
106 sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
107 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
110 sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
111 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
114 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
115 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
118 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
119 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
121 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
122 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
123 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
124 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
125 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
126 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
128 #error Unsupported console port number. Please fix pin mux settings in board.c
134 int spl_board_load_image(void)
136 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
137 return_to_fel(fel_stash.sp, fel_stash.lr);
145 * Undocumented magic taken from boot0, without this DRAM
146 * access gets messed up (seems cache related).
147 * The boot0 sources describe this as: "config ema for cache sram"
149 #if defined CONFIG_MACH_SUN6I
150 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
151 #elif defined CONFIG_MACH_SUN8I
152 __maybe_unused uint version;
154 /* Unlock sram version info reg, read it, relock */
155 setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
156 version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
157 clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
160 * Ideally this would be a switch case, but we do not know exactly
161 * which versions there are and which version needs which settings,
162 * so reproduce the per SoC code from the BSP.
164 #if defined CONFIG_MACH_SUN8I_A23
165 if (version == 0x1650)
166 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
168 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
169 #elif defined CONFIG_MACH_SUN8I_A33
170 if (version != 0x1667)
171 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
173 /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
174 /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
177 #if defined CONFIG_MACH_SUN6I || \
178 defined CONFIG_MACH_SUN7I || \
179 defined CONFIG_MACH_SUN8I
180 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
182 "mrc p15, 0, r0, c1, c0, 1\n"
183 "orr r0, r0, #1 << 6\n"
184 "mcr p15, 0, r0, c1, c0, 1\n");
186 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
187 /* Enable non-secure access to some peripherals */
198 #ifdef CONFIG_SPL_BUILD
199 DECLARE_GLOBAL_DATA_PTR;
201 /* The sunxi internal brom will try to loader external bootloader
202 * from mmc0, nand flash, mmc2.
204 u32 spl_boot_device(void)
206 __maybe_unused struct mmc *mmc0, *mmc1;
208 * When booting from the SD card or NAND memory, the "eGON.BT0"
209 * signature is expected to be found in memory at the address 0x0004
210 * (see the "mksunxiboot" tool, which generates this header).
212 * When booting in the FEL mode over USB, this signature is patched in
213 * memory and replaced with something else by the 'fel' tool. This other
214 * signature is selected in such a way, that it can't be present in a
215 * valid bootable SD card image (because the BROM would refuse to
216 * execute the SPL in this case).
218 * This checks for the signature and if it is not found returns to
219 * the FEL code in the BROM to wait and receive the main u-boot
220 * binary over USB. If it is found, it determines where SPL was
223 if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
224 return BOOT_DEVICE_BOARD;
226 /* The BROM will try to boot from mmc0 first, so try that first. */
228 mmc_initialize(gd->bd);
229 mmc0 = find_mmc_device(0);
230 if (sunxi_mmc_has_egon_boot_signature(mmc0))
231 return BOOT_DEVICE_MMC1;
234 /* Fallback to booting NAND if enabled. */
235 if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
236 return BOOT_DEVICE_NAND;
239 if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
240 mmc1 = find_mmc_device(1);
241 if (sunxi_mmc_has_egon_boot_signature(mmc1))
242 return BOOT_DEVICE_MMC2;
246 panic("Could not determine boot source\n");
247 return -1; /* Never reached */
251 * Properly announce BOOT_DEVICE_BOARD as "FEL".
252 * Overrides weak function from common/spl/spl.c
254 void spl_board_announce_boot_device(void)
259 /* No confirmation data available in SPL yet. Hardcode bootmode */
260 u32 spl_boot_mode(void)
262 return MMCSD_MODE_RAW;
265 void board_init_f(ulong dummy)
268 preloader_console_init();
270 #ifdef CONFIG_SPL_I2C_SUPPORT
271 /* Needed early by sunxi_board_init if PMU is enabled */
272 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
278 void reset_cpu(ulong addr)
280 #ifdef CONFIG_SUNXI_GEN_SUN4I
281 static const struct sunxi_wdog *wdog =
282 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
284 /* Set the watchdog for its shortest interval (.5s) and wait */
285 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
286 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
289 /* sun5i sometimes gets stuck without this */
290 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
293 #ifdef CONFIG_SUNXI_GEN_SUN6I
294 static const struct sunxi_wdog *wdog =
295 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
297 /* Set the watchdog for its shortest interval (.5s) and wait */
298 writel(WDT_CFG_RESET, &wdog->cfg);
299 writel(WDT_MODE_EN, &wdog->mode);
300 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
305 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
306 void enable_caches(void)
308 /* Enable D-cache. I-cache is already enabled in start.S */