git.sur5r.net Git - u-boot/blob - arch/arm/mach-sunxi/clock_sun4i.c

   1 /*
   2  * sun4i, sun5i and sun7i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24
  25         /* Set safe defaults until PMU is configured */
  26         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
  27                AHB_DIV_2 << AHB_DIV_SHIFT |
  28                APB0_DIV_1 << APB0_DIV_SHIFT |
  29                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
  30                &ccm->cpu_ahb_apb0_cfg);
  31         writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
  32         sdelay(200);
  33         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
  34                AHB_DIV_2 << AHB_DIV_SHIFT |
  35                APB0_DIV_1 << APB0_DIV_SHIFT |
  36                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
  37                &ccm->cpu_ahb_apb0_cfg);
  38 #ifdef CONFIG_MACH_SUN7I
  39         setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
  40 #endif
  41         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  42 #ifdef CONFIG_SUNXI_AHCI
  43         setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
  44         setbits_le32(&ccm->pll6_cfg, 0x1 << CCM_PLL6_CTRL_SATA_EN_SHIFT);
  45 #endif
  46 }
  47 #endif
  48
  49 void clock_init_uart(void)
  50 {
  51         struct sunxi_ccm_reg *const ccm =
  52                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  53
  54         /* uart clock source is apb1 */
  55         writel(APB1_CLK_SRC_OSC24M|
  56                APB1_CLK_RATE_N_1|
  57                APB1_CLK_RATE_M(1),
  58                &ccm->apb1_clk_div_cfg);
  59
  60         /* open the clock for uart */
  61         setbits_le32(&ccm->apb1_gate,
  62                 CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX - 1));
  63 }
  64
  65 int clock_twi_onoff(int port, int state)
  66 {
  67         struct sunxi_ccm_reg *const ccm =
  68                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  69
  70         /* set the apb clock gate for twi */
  71         if (state)
  72                 setbits_le32(&ccm->apb1_gate,
  73                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
  74         else
  75                 clrbits_le32(&ccm->apb1_gate,
  76                              CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
  77
  78         return 0;
  79 }
  80
  81 #ifdef CONFIG_SPL_BUILD
  82 #define PLL1_CFG(N, K, M, P)    ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
  83                                   0 << CCM_PLL1_CFG_VCO_RST_SHIFT |  \
  84                                   8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
  85                                   0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
  86                                  16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
  87                                  (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
  88                                   2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
  89                                  (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
  90                                  (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
  91                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
  92                                   0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
  93                                  (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
  94
  95 static struct {
  96         u32 pll1_cfg;
  97         unsigned int freq;
  98 } pll1_para[] = {
  99         /* This array must be ordered by frequency. */
 100         { PLL1_CFG(31, 1, 0, 0), 1488000000},
 101         { PLL1_CFG(30, 1, 0, 0), 1440000000},
 102         { PLL1_CFG(29, 1, 0, 0), 1392000000},
 103         { PLL1_CFG(28, 1, 0, 0), 1344000000},
 104         { PLL1_CFG(27, 1, 0, 0), 1296000000},
 105         { PLL1_CFG(26, 1, 0, 0), 1248000000},
 106         { PLL1_CFG(25, 1, 0, 0), 1200000000},
 107         { PLL1_CFG(24, 1, 0, 0), 1152000000},
 108         { PLL1_CFG(23, 1, 0, 0), 1104000000},
 109         { PLL1_CFG(22, 1, 0, 0), 1056000000},
 110         { PLL1_CFG(21, 1, 0, 0), 1008000000},
 111         { PLL1_CFG(20, 1, 0, 0), 960000000 },
 112         { PLL1_CFG(19, 1, 0, 0), 912000000 },
 113         { PLL1_CFG(16, 1, 0, 0), 768000000 },
 114         /* Final catchall entry 384MHz*/
 115         { PLL1_CFG(16, 0, 0, 0), 0 },
 116
 117 };
 118
 119 void clock_set_pll1(unsigned int hz)
 120 {
 121         int i = 0;
 122         int axi, ahb, apb0;
 123         struct sunxi_ccm_reg * const ccm =
 124                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 125
 126         /* Find target frequency */
 127         while (pll1_para[i].freq > hz)
 128                 i++;
 129
 130         hz = pll1_para[i].freq;
 131         if (! hz)
 132                 hz = 384000000;
 133
 134         /* Calculate system clock divisors */
 135         axi = DIV_ROUND_UP(hz, 432000000);      /* Max 450MHz */
 136         ahb = DIV_ROUND_UP(hz/axi, 204000000);  /* Max 250MHz */
 137         apb0 = 2;                               /* Max 150MHz */
 138
 139         printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
 140
 141         /* Map divisors to register values */
 142         axi = axi - 1;
 143         if (ahb > 4)
 144                 ahb = 3;
 145         else if (ahb > 2)
 146                 ahb = 2;
 147         else if (ahb > 1)
 148                 ahb = 1;
 149         else
 150                 ahb = 0;
 151
 152         apb0 = apb0 - 1;
 153
 154         /* Switch to 24MHz clock while changing PLL1 */
 155         writel(AXI_DIV_1 << AXI_DIV_SHIFT |
 156                AHB_DIV_2 << AHB_DIV_SHIFT |
 157                APB0_DIV_1 << APB0_DIV_SHIFT |
 158                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 159                &ccm->cpu_ahb_apb0_cfg);
 160         sdelay(20);
 161
 162         /* Configure sys clock divisors */
 163         writel(axi << AXI_DIV_SHIFT |
 164                ahb << AHB_DIV_SHIFT |
 165                apb0 << APB0_DIV_SHIFT |
 166                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 167                &ccm->cpu_ahb_apb0_cfg);
 168
 169         /* Configure PLL1 at the desired frequency */
 170         writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
 171         sdelay(200);
 172
 173         /* Switch CPU to PLL1 */
 174         writel(axi << AXI_DIV_SHIFT |
 175                ahb << AHB_DIV_SHIFT |
 176                apb0 << APB0_DIV_SHIFT |
 177                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 178                &ccm->cpu_ahb_apb0_cfg);
 179         sdelay(20);
 180 }
 181 #endif
 182
 183 void clock_set_pll3(unsigned int clk)
 184 {
 185         struct sunxi_ccm_reg * const ccm =
 186                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 187
 188         if (clk == 0) {
 189                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 190                 return;
 191         }
 192
 193         /* PLL3 rate = 3000000 * m */
 194         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 195                CCM_PLL3_CTRL_M(clk / 3000000), &ccm->pll3_cfg);
 196 }
 197
 198 unsigned int clock_get_pll3(void)
 199 {
 200         struct sunxi_ccm_reg *const ccm =
 201                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 202         uint32_t rval = readl(&ccm->pll3_cfg);
 203         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT);
 204         return 3000000 * m;
 205 }
 206
 207 unsigned int clock_get_pll5p(void)
 208 {
 209         struct sunxi_ccm_reg *const ccm =
 210                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 211         uint32_t rval = readl(&ccm->pll5_cfg);
 212         int n = ((rval & CCM_PLL5_CTRL_N_MASK) >> CCM_PLL5_CTRL_N_SHIFT);
 213         int k = ((rval & CCM_PLL5_CTRL_K_MASK) >> CCM_PLL5_CTRL_K_SHIFT) + 1;
 214         int p = ((rval & CCM_PLL5_CTRL_P_MASK) >> CCM_PLL5_CTRL_P_SHIFT);
 215         return (24000000 * n * k) >> p;
 216 }
 217
 218 unsigned int clock_get_pll6(void)
 219 {
 220         struct sunxi_ccm_reg *const ccm =
 221                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 222         uint32_t rval = readl(&ccm->pll6_cfg);
 223         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
 224         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 225         return 24000000 * n * k / 2;
 226 }
 227
 228 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 229 {
 230         int pll = clock_get_pll5p();
 231         int div = 1;
 232
 233         while ((pll / div) > hz)
 234                 div++;
 235
 236         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_RST | CCM_DE_CTRL_PLL5P |
 237                CCM_DE_CTRL_M(div), clk_cfg);
 238 }