2 * sun6i specific clock code
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/prcm.h>
17 #include <asm/arch/sys_proto.h>
19 #ifdef CONFIG_SPL_BUILD
20 void clock_init_safe(void)
22 struct sunxi_ccm_reg * const ccm =
23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25 #if !defined(CONFIG_MACH_SUN8I_H3) && !defined(CONFIG_MACH_SUN50I)
26 struct sunxi_prcm_reg * const prcm =
27 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
29 /* Set PLL ldo voltage without this PLL6 does not work properly */
30 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
31 PRCM_PLL_CTRL_LDO_KEY);
32 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
33 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
34 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
35 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
38 clock_set_pll1(408000000);
40 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
41 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
44 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
46 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
47 if (IS_ENABLED(CONFIG_MACH_SUN6I))
48 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
52 void clock_init_sec(void)
54 #ifdef CONFIG_MACH_SUN8I_H3
55 struct sunxi_ccm_reg * const ccm =
56 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
58 setbits_le32(&ccm->ccu_sec_switch,
59 CCM_SEC_SWITCH_MBUS_NONSEC |
60 CCM_SEC_SWITCH_BUS_NONSEC |
61 CCM_SEC_SWITCH_PLL_NONSEC);
65 void clock_init_uart(void)
67 #if CONFIG_CONS_INDEX < 5
68 struct sunxi_ccm_reg *const ccm =
69 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
71 /* uart clock source is apb2 */
72 writel(APB2_CLK_SRC_OSC24M|
77 /* open the clock for uart */
78 setbits_le32(&ccm->apb2_gate,
79 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
80 CONFIG_CONS_INDEX - 1));
82 /* deassert uart reset */
83 setbits_le32(&ccm->apb2_reset_cfg,
84 1 << (APB2_RESET_UART_SHIFT +
85 CONFIG_CONS_INDEX - 1));
87 /* enable R_PIO and R_UART clocks, and de-assert resets */
88 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
92 #ifdef CONFIG_SPL_BUILD
93 void clock_set_pll1(unsigned int clk)
95 struct sunxi_ccm_reg * const ccm =
96 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
101 if (clk > 1152000000) {
103 } else if (clk > 768000000) {
108 /* Switch to 24MHz clock while changing PLL1 */
109 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
110 ATB_DIV_2 << ATB_DIV_SHIFT |
111 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
115 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
116 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
118 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
119 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
120 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
123 /* Switch CPU to PLL1 */
124 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
125 ATB_DIV_2 << ATB_DIV_SHIFT |
126 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
131 void clock_set_pll3(unsigned int clk)
133 struct sunxi_ccm_reg * const ccm =
134 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
135 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
138 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
142 /* PLL3 rate = 24000000 * n / m */
143 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
144 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
148 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
150 struct sunxi_ccm_reg * const ccm =
151 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
152 const int max_n = 32;
155 #ifdef CONFIG_MACH_SUN8I_H3
156 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
157 CCM_PLL5_TUN_INIT_FREQ_MASK,
158 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
161 if (sigma_delta_enable)
162 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
164 /* PLL5 rate = 24000000 * n * k / m */
165 if (clk > 24000000 * k * max_n / m) {
167 if (clk > 24000000 * k * max_n / m)
170 writel(CCM_PLL5_CTRL_EN |
171 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
173 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
174 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
179 #ifdef CONFIG_MACH_SUN6I
180 void clock_set_mipi_pll(unsigned int clk)
182 struct sunxi_ccm_reg * const ccm =
183 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
184 unsigned int k, m, n, value, diff;
185 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
186 unsigned int src = clock_get_pll3();
188 /* All calculations are in KHz to avoid overflows */
192 /* Pick the closest lower clock */
193 for (k = 1; k <= 4; k++) {
194 for (m = 1; m <= 16; m++) {
195 for (n = 1; n <= 16; n++) {
196 value = src * n * k / m;
201 if (diff < best_diff) {
214 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
215 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
216 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
220 #if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
221 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
223 struct sunxi_ccm_reg * const ccm =
224 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
226 if (sigma_delta_enable)
227 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
229 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
230 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
231 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
233 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
238 unsigned int clock_get_pll3(void)
240 struct sunxi_ccm_reg *const ccm =
241 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
242 uint32_t rval = readl(&ccm->pll3_cfg);
243 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
244 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
246 /* Multiply by 1000 after dividing by m to avoid integer overflows */
247 return (24000 * n / m) * 1000;
250 unsigned int clock_get_pll6(void)
252 struct sunxi_ccm_reg *const ccm =
253 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
254 uint32_t rval = readl(&ccm->pll6_cfg);
255 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
256 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
257 return 24000000 * n * k / 2;
260 unsigned int clock_get_mipi_pll(void)
262 struct sunxi_ccm_reg *const ccm =
263 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
264 uint32_t rval = readl(&ccm->mipi_pll_cfg);
265 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
266 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
267 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
268 unsigned int src = clock_get_pll3();
270 /* Multiply by 1000 after dividing by m to avoid integer overflows */
271 return ((src / 1000) * n * k / m) * 1000;
274 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
276 int pll = clock_get_pll6() * 2;
279 while ((pll / div) > hz)
282 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),