git.sur5r.net Git - u-boot/blob - arch/arm/mach-sunxi/clock_sun6i.c

   1 /*
   2  * sun6i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24         struct sunxi_prcm_reg * const prcm =
  25                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  26
  27         /* Set PLL ldo voltage without this PLL6 does not work properly */
  28         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  29                         PRCM_PLL_CTRL_LDO_KEY);
  30         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  31                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  32                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  33         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  34
  35         clock_set_pll1(408000000);
  36
  37         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  38         while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
  39                 ;
  40
  41         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  42
  43         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  44         writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
  45 }
  46 #endif
  47
  48 void clock_init_sec(void)
  49 {
  50 #ifdef CONFIG_MACH_SUN8I_H3
  51         struct sunxi_ccm_reg * const ccm =
  52                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  53
  54         setbits_le32(&ccm->ccu_sec_switch,
  55                      CCM_SEC_SWITCH_MBUS_NONSEC |
  56                      CCM_SEC_SWITCH_BUS_NONSEC |
  57                      CCM_SEC_SWITCH_PLL_NONSEC);
  58 #endif
  59 }
  60
  61 void clock_init_uart(void)
  62 {
  63 #if CONFIG_CONS_INDEX < 5
  64         struct sunxi_ccm_reg *const ccm =
  65                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  66
  67         /* uart clock source is apb2 */
  68         writel(APB2_CLK_SRC_OSC24M|
  69                APB2_CLK_RATE_N_1|
  70                APB2_CLK_RATE_M(1),
  71                &ccm->apb2_div);
  72
  73         /* open the clock for uart */
  74         setbits_le32(&ccm->apb2_gate,
  75                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  76                                        CONFIG_CONS_INDEX - 1));
  77
  78         /* deassert uart reset */
  79         setbits_le32(&ccm->apb2_reset_cfg,
  80                      1 << (APB2_RESET_UART_SHIFT +
  81                            CONFIG_CONS_INDEX - 1));
  82 #else
  83         /* enable R_PIO and R_UART clocks, and de-assert resets */
  84         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
  85 #endif
  86 }
  87
  88 #ifdef CONFIG_SPL_BUILD
  89 void clock_set_pll1(unsigned int clk)
  90 {
  91         struct sunxi_ccm_reg * const ccm =
  92                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  93         const int p = 0;
  94         int k = 1;
  95         int m = 1;
  96
  97         if (clk > 1152000000) {
  98                 k = 2;
  99         } else if (clk > 768000000) {
 100                 k = 3;
 101                 m = 2;
 102         }
 103
 104         /* Switch to 24MHz clock while changing PLL1 */
 105         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 106                ATB_DIV_2 << ATB_DIV_SHIFT |
 107                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 108                &ccm->cpu_axi_cfg);
 109
 110         /*
 111          * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m   (p is ignored)
 112          * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
 113          */
 114         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
 115                CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 116                CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 117         sdelay(200);
 118
 119         /* Switch CPU to PLL1 */
 120         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 121                ATB_DIV_2 << ATB_DIV_SHIFT |
 122                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 123                &ccm->cpu_axi_cfg);
 124 }
 125 #endif
 126
 127 void clock_set_pll3(unsigned int clk)
 128 {
 129         struct sunxi_ccm_reg * const ccm =
 130                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 131         const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
 132
 133         if (clk == 0) {
 134                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 135                 return;
 136         }
 137
 138         /* PLL3 rate = 24000000 * n / m */
 139         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 140                CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
 141                &ccm->pll3_cfg);
 142 }
 143
 144 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 145 {
 146         struct sunxi_ccm_reg * const ccm =
 147                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 148         const int max_n = 32;
 149         int k = 1, m = 2;
 150
 151         if (sigma_delta_enable)
 152                 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 153
 154         /* PLL5 rate = 24000000 * n * k / m */
 155         if (clk > 24000000 * k * max_n / m) {
 156                 m = 1;
 157                 if (clk > 24000000 * k * max_n / m)
 158                         k = 2;
 159         }
 160         writel(CCM_PLL5_CTRL_EN |
 161                (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
 162                CCM_PLL5_CTRL_UPD |
 163                CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 164                CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 165
 166         udelay(5500);
 167 }
 168
 169 #ifdef CONFIG_MACH_SUN6I
 170 void clock_set_mipi_pll(unsigned int clk)
 171 {
 172         struct sunxi_ccm_reg * const ccm =
 173                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 174         unsigned int k, m, n, value, diff;
 175         unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
 176         unsigned int src = clock_get_pll3();
 177
 178         /* All calculations are in KHz to avoid overflows */
 179         clk /= 1000;
 180         src /= 1000;
 181
 182         /* Pick the closest lower clock */
 183         for (k = 1; k <= 4; k++) {
 184                 for (m = 1; m <= 16; m++) {
 185                         for (n = 1; n <= 16; n++) {
 186                                 value = src * n * k / m;
 187                                 if (value > clk)
 188                                         continue;
 189
 190                                 diff = clk - value;
 191                                 if (diff < best_diff) {
 192                                         best_diff = diff;
 193                                         best_k = k;
 194                                         best_m = m;
 195                                         best_n = n;
 196                                 }
 197                                 if (diff == 0)
 198                                         goto done;
 199                         }
 200                 }
 201         }
 202
 203 done:
 204         writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
 205                CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
 206                CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
 207 }
 208 #endif
 209
 210 #ifdef CONFIG_MACH_SUN8I_A33
 211 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 212 {
 213         struct sunxi_ccm_reg * const ccm =
 214                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 215
 216         if (sigma_delta_enable)
 217                 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
 218
 219         writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
 220                (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
 221                CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
 222
 223         while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
 224                 ;
 225 }
 226 #endif
 227
 228 unsigned int clock_get_pll3(void)
 229 {
 230         struct sunxi_ccm_reg *const ccm =
 231                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 232         uint32_t rval = readl(&ccm->pll3_cfg);
 233         int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
 234         int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
 235
 236         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 237         return (24000 * n / m) * 1000;
 238 }
 239
 240 unsigned int clock_get_pll6(void)
 241 {
 242         struct sunxi_ccm_reg *const ccm =
 243                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 244         uint32_t rval = readl(&ccm->pll6_cfg);
 245         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 246         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 247         return 24000000 * n * k / 2;
 248 }
 249
 250 unsigned int clock_get_mipi_pll(void)
 251 {
 252         struct sunxi_ccm_reg *const ccm =
 253                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 254         uint32_t rval = readl(&ccm->mipi_pll_cfg);
 255         unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
 256         unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
 257         unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
 258         unsigned int src = clock_get_pll3();
 259
 260         /* Multiply by 1000 after dividing by m to avoid integer overflows */
 261         return ((src / 1000) * n * k / m) * 1000;
 262 }
 263
 264 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 265 {
 266         int pll = clock_get_pll6() * 2;
 267         int div = 1;
 268
 269         while ((pll / div) > hz)
 270                 div++;
 271
 272         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 273                clk_cfg);
 274 }