git.sur5r.net Git - u-boot/blob - arch/arm/mach-sunxi/p2wi.c

   1 /*
   2  * Sunxi A31 Power Management Unit
   3  *
   4  * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
   5  * http://linux-sunxi.org
   6  *
   7  * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
   8  *
   9  * (C) Copyright 2006-2013
  10  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  11  * Berg Xing <bergxing@allwinnertech.com>
  12  * Tom Cubie <tangliang@allwinnertech.com>
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <common.h>
  18 #include <errno.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/p2wi.h>
  23 #include <asm/arch/prcm.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/sys_proto.h>
  26
  27 void p2wi_init(void)
  28 {
  29         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  30
  31         /* Enable p2wi and PIO clk, and de-assert their resets */
  32         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
  33
  34         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
  35         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
  36
  37         /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
  38         writel(P2WI_CTRL_RESET, &p2wi->ctrl);
  39         sdelay(0x100);
  40         writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
  41                &p2wi->cc);
  42 }
  43
  44 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
  45 {
  46         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  47         unsigned long tmo = timer_get_us() + 1000000;
  48
  49         writel(P2WI_PM_DEV_ADDR(slave_addr) |
  50                P2WI_PM_CTRL_ADDR(ctrl_reg) |
  51                P2WI_PM_INIT_DATA(init_data) |
  52                P2WI_PM_INIT_SEND,
  53                &p2wi->pm);
  54
  55         while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
  56                 if (timer_get_us() > tmo)
  57                         return -ETIME;
  58         }
  59
  60         return 0;
  61 }
  62
  63 static int p2wi_await_trans(void)
  64 {
  65         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  66         unsigned long tmo = timer_get_us() + 1000000;
  67         int ret;
  68         u8 reg;
  69
  70         while (1) {
  71                 reg = readl(&p2wi->status);
  72                 if (reg & P2WI_STAT_TRANS_ERR) {
  73                         ret = -EIO;
  74                         break;
  75                 }
  76                 if (reg & P2WI_STAT_TRANS_DONE) {
  77                         ret = 0;
  78                         break;
  79                 }
  80                 if (timer_get_us() > tmo) {
  81                         ret = -ETIME;
  82                         break;
  83                 }
  84         }
  85         writel(reg, &p2wi->status); /* Clear status bits */
  86         return ret;
  87 }
  88
  89 int p2wi_read(const u8 addr, u8 *data)
  90 {
  91         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
  92         int ret;
  93
  94         writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
  95         writel(P2WI_DATA_NUM_BYTES(1) |
  96                P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
  97         writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
  98         writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
  99
 100         ret = p2wi_await_trans();
 101
 102         *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
 103         return ret;
 104 }
 105
 106 int p2wi_write(const u8 addr, u8 data)
 107 {
 108         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
 109
 110         writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
 111         writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
 112         writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
 113         writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
 114         writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
 115
 116         return p2wi_await_trans();
 117 }