4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/usb_phy.h>
21 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
22 #ifdef CONFIG_MACH_SUN8I_A33
23 #define SUNXI_USB_CSR 0x410
25 #define SUNXI_USB_CSR 0x404
27 #define SUNXI_USB_PASSBY_EN 1
29 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
30 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
31 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
32 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
34 #define REG_PHY_UNK_H3 0x420
35 #define REG_PMU_UNK_H3 0x810
37 /* A83T specific control bits for PHY0 */
38 #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5)
39 #define SUNXI_PHY_CTL_SIDDQ BIT(3)
41 /* A83T HSIC specific bits */
42 #define SUNXI_EHCI_HS_FORCE BIT(20)
43 #define SUNXI_EHCI_CONNECT_DET BIT(17)
44 #define SUNXI_EHCI_CONNECT_INT BIT(16)
45 #define SUNXI_EHCI_HSIC BIT(1)
47 static struct sunxi_usb_phy {
58 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
60 .base = SUNXI_USB0_BASE,
63 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
65 .base = SUNXI_USB1_BASE,
67 #if CONFIG_SUNXI_USB_PHYS >= 3
69 #ifdef CONFIG_MACH_SUN8I_A83T
70 .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
73 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
76 .base = SUNXI_USB2_BASE,
79 #if CONFIG_SUNXI_USB_PHYS >= 4
81 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
83 .base = SUNXI_USB3_BASE,
88 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
90 static int get_vbus_gpio(int index)
93 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
94 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
95 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
96 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
101 static int get_vbus_detect_gpio(int index)
104 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
109 static int get_id_detect_gpio(int index)
112 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
117 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
120 int j = 0, usbc_bit = 0;
121 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
123 #ifdef CONFIG_MACH_SUN8I_A33
124 /* CSR needs to be explicitly initialized to 0 on A33 */
128 usbc_bit = 1 << (phy->id * 2);
129 for (j = 0; j < len; j++) {
130 /* set the bit address to be written */
131 clrbits_le32(dest, 0xff << 8);
132 setbits_le32(dest, (addr + j) << 8);
134 clrbits_le32(dest, usbc_bit);
137 setbits_le32(dest, 1 << 7);
139 clrbits_le32(dest, 1 << 7);
141 setbits_le32(dest, usbc_bit);
143 clrbits_le32(dest, usbc_bit);
149 #if defined CONFIG_MACH_SUN8I_H3
150 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
153 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
155 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
157 #elif defined CONFIG_MACH_SUN8I_A83T
158 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
162 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
164 /* The following comments are machine
165 * translated from Chinese, you have been warned!
168 /* Regulation 45 ohms */
170 usb_phy_write(phy, 0x0c, 0x01, 1);
172 /* adjust PHY's magnitude and rate */
173 usb_phy_write(phy, 0x20, 0x14, 5);
175 /* threshold adjustment disconnect */
176 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
177 usb_phy_write(phy, 0x2a, 2, 2);
179 usb_phy_write(phy, 0x2a, 3, 2);
186 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
188 unsigned long bits = 0;
191 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
193 bits = SUNXI_EHCI_AHB_ICHR8_EN |
194 SUNXI_EHCI_AHB_INCR4_BURST_EN |
195 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
196 SUNXI_EHCI_ULPI_BYPASS_EN;
198 #ifdef CONFIG_MACH_SUN8I_A83T
200 bits |= SUNXI_EHCI_HS_FORCE |
201 SUNXI_EHCI_CONNECT_INT |
206 setbits_le32(addr, bits);
208 clrbits_le32(addr, bits);
213 void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
215 #ifndef CONFIG_MACH_SUN8I_A83T
216 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
218 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
222 void sunxi_usb_phy_init(int index)
224 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
225 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
228 if (phy->init_count != 1)
231 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
233 sunxi_usb_phy_config(phy);
236 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
238 #ifdef CONFIG_MACH_SUN8I_A83T
240 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
241 SUNXI_PHY_CTL_VBUSVLDEXT);
242 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
243 SUNXI_PHY_CTL_SIDDQ);
248 void sunxi_usb_phy_exit(int index)
250 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
251 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
254 if (phy->init_count != 0)
258 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
260 #ifdef CONFIG_MACH_SUN8I_A83T
262 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
263 SUNXI_PHY_CTL_SIDDQ);
267 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
270 void sunxi_usb_phy_power_on(int index)
272 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
274 if (initial_usb_scan_delay) {
275 mdelay(initial_usb_scan_delay);
276 initial_usb_scan_delay = 0;
279 phy->power_on_count++;
280 if (phy->power_on_count != 1)
283 if (phy->gpio_vbus >= 0)
284 gpio_set_value(phy->gpio_vbus, 1);
287 void sunxi_usb_phy_power_off(int index)
289 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
291 phy->power_on_count--;
292 if (phy->power_on_count != 0)
295 if (phy->gpio_vbus >= 0)
296 gpio_set_value(phy->gpio_vbus, 0);
299 int sunxi_usb_phy_power_is_on(int index)
301 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
303 return phy->power_on_count > 0;
306 int sunxi_usb_phy_vbus_detect(int index)
308 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
309 int err, retries = 3;
311 if (phy->gpio_vbus_det < 0)
312 return phy->gpio_vbus_det;
314 err = gpio_get_value(phy->gpio_vbus_det);
316 * Vbus may have been provided by the board and just been turned of
317 * some milliseconds ago on reset, what we're measuring then is a
318 * residual charge on Vbus, sleep a bit and try again.
320 while (err > 0 && retries--) {
322 err = gpio_get_value(phy->gpio_vbus_det);
328 int sunxi_usb_phy_id_detect(int index)
330 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
332 if (phy->gpio_id_det < 0)
333 return phy->gpio_id_det;
335 return gpio_get_value(phy->gpio_id_det);
338 int sunxi_usb_phy_probe(void)
340 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
341 struct sunxi_usb_phy *phy;
344 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
345 phy = &sunxi_usb_phy[i];
347 phy->gpio_vbus = get_vbus_gpio(i);
348 if (phy->gpio_vbus >= 0) {
349 ret = gpio_request(phy->gpio_vbus, "usb_vbus");
352 ret = gpio_direction_output(phy->gpio_vbus, 0);
357 phy->gpio_vbus_det = get_vbus_detect_gpio(i);
358 if (phy->gpio_vbus_det >= 0) {
359 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
362 ret = gpio_direction_input(phy->gpio_vbus_det);
367 phy->gpio_id_det = get_id_detect_gpio(i);
368 if (phy->gpio_id_det >= 0) {
369 ret = gpio_request(phy->gpio_id_det, "usb_id_det");
372 ret = gpio_direction_input(phy->gpio_id_det);
375 sunxi_gpio_set_pull(phy->gpio_id_det,
380 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
385 int sunxi_usb_phy_remove(void)
387 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
388 struct sunxi_usb_phy *phy;
391 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
393 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
394 phy = &sunxi_usb_phy[i];
396 if (phy->gpio_vbus >= 0)
397 gpio_free(phy->gpio_vbus);
399 if (phy->gpio_vbus_det >= 0)
400 gpio_free(phy->gpio_vbus_det);
402 if (phy->gpio_id_det >= 0)
403 gpio_free(phy->gpio_id_det);