2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 /* Tegra AP (Application Processor) code */
12 #include <asm/arch/gp_padctrl.h>
13 #include <asm/arch/mc.h>
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/clock.h>
16 #include <asm/arch-tegra/fuse.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/scu.h>
19 #include <asm/arch-tegra/tegra.h>
20 #include <asm/arch-tegra/warmboot.h>
22 int tegra_get_chip(void)
25 struct apb_misc_gp_ctlr *gp =
26 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
29 * This is undocumented, Chip ID is bits 15:8 of the register
30 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
31 * Tegra30, 0x35 for T114, and 0x40 for Tegra124.
33 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
34 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
39 int tegra_get_sku_info(void)
42 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
44 sku_id = readl(&fuse->sku_info) & 0xff;
45 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
50 int tegra_get_chip_sku(void)
54 chip_id = tegra_get_chip();
55 sku_id = tegra_get_sku_info();
75 case SKU_ID_TM30MQS_P_A3:
85 return TEGRA_SOC_T114;
92 return TEGRA_SOC_T124;
97 /* unknown chip/sku id */
98 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
99 __func__, chip_id, sku_id);
100 return TEGRA_SOC_UNKNOWN;
103 static void enable_scu(void)
105 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
108 /* Only enable the SCU on T20/T25 */
109 if (tegra_get_chip() != CHIPID_TEGRA20)
112 /* If SCU already setup/enabled, return */
113 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
116 /* Invalidate all ways for all processors */
117 writel(0xFFFF, &scu->scu_inv_all);
119 /* Enable SCU - bit 0 */
120 reg = readl(&scu->scu_ctrl);
121 reg |= SCU_CTRL_ENABLE;
122 writel(reg, &scu->scu_ctrl);
125 static u32 get_odmdata(void)
128 * ODMDATA is stored in the BCT in IRAM by the BootROM.
129 * The BCT start and size are stored in the BIT in IRAM.
130 * Read the data @ bct_start + (bct_size - 12). This works
131 * on BCTs for currently supported SoCs, which are locked down.
132 * If this changes in new chips, we can revisit this algorithm.
135 u32 bct_start, odmdata;
137 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
138 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
143 static void init_pmc_scratch(void)
145 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
149 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
150 for (i = 0; i < 23; i++)
151 writel(0, &pmc->pmc_scratch1+i);
153 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
154 odmdata = get_odmdata();
155 writel(odmdata, &pmc->pmc_scratch20);
158 #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE
159 void protect_secure_section(void)
161 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
163 /* Must be MB aligned */
164 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_BASE & 0xFFFFF);
165 BUILD_BUG_ON(CONFIG_ARMV7_SECURE_RESERVE_SIZE & 0xFFFFF);
167 writel(CONFIG_ARMV7_SECURE_BASE, &mc->mc_security_cfg0);
168 writel(CONFIG_ARMV7_SECURE_RESERVE_SIZE >> 20, &mc->mc_security_cfg1);
172 #if defined(CONFIG_ARMV7_NONSEC)
173 static void smmu_flush(struct mc_ctlr *mc)
175 (void)readl(&mc->mc_smmu_config);
178 static void smmu_enable(void)
180 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
184 * Enable translation for all clients since access to this register
185 * is restricted to TrustZone-secured requestors. The kernel will use
186 * the per-SWGROUP enable bits to enable or disable translations.
188 writel(0xffffffff, &mc->mc_smmu_translation_enable_0);
189 writel(0xffffffff, &mc->mc_smmu_translation_enable_1);
190 writel(0xffffffff, &mc->mc_smmu_translation_enable_2);
191 writel(0xffffffff, &mc->mc_smmu_translation_enable_3);
194 * Enable SMMU globally since access to this register is restricted
195 * to TrustZone-secured requestors.
197 value = readl(&mc->mc_smmu_config);
198 value |= TEGRA_MC_SMMU_CONFIG_ENABLE;
199 writel(value, &mc->mc_smmu_config);
204 static void smmu_enable(void)
211 /* Init PMC scratch memory */