2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
6 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define SECTION_SHIFT_L1 30UL
18 #define SECTION_SHIFT_L2 21UL
19 #define BLOCK_SIZE_L0 0x8000000000UL
20 #define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
21 #define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
23 #define TCR_TG1_4K (1 << 31)
24 #define TCR_EPD1_DISABLE (1 << 23)
25 #define TEGRA_VA_BITS 40
26 #define TEGRA_TCR TCR_TG1_4K | \
32 TCR_T0SZ(TEGRA_VA_BITS)
34 #define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \
35 PMD_ATTRINDX(MT_NORMAL) | \
37 #define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \
38 PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
41 /* 4K size is required to place 512 entries in each level */
42 #define TLB_TABLE_SIZE 0x1000
45 * This mmu table looks as below
46 * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
47 * and other Level1 Table1.
48 * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
49 * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
50 * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
51 * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
56 u64 i, section_l1t0, section_l1t1;
57 u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
58 u64 *level0_table = (u64 *)gd->arch.tlb_addr;
59 u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
60 u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
61 u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
62 u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
63 u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
64 u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
66 /* Invalidate all table entries */
67 memset(level0_table, 0, PGTABLE_SIZE);
70 (u64)level1_table_0 | PMD_TYPE_TABLE;
72 (u64)level1_table_1 | PMD_TYPE_TABLE;
75 * set level 1 table 0, covering 0 to 512GB
76 * set level 1 table 1, covering 512GB to 1TB
79 section_l1t1 = BLOCK_SIZE_L0;
81 for (i = 0; i < 512; i++) {
82 level1_table_0[i] = section_l1t0;
84 level1_table_0[i] |= MEMORY_ATTR;
85 level1_table_1[i] = section_l1t1;
86 level1_table_1[i] |= MEMORY_ATTR;
87 section_l1t0 += BLOCK_SIZE_L1;
88 section_l1t1 += BLOCK_SIZE_L1;
92 (u64)level2_table_0 | PMD_TYPE_TABLE;
94 (u64)level2_table_1 | PMD_TYPE_TABLE;
96 (u64)level2_table_2 | PMD_TYPE_TABLE;
98 (u64)level2_table_3 | PMD_TYPE_TABLE;
101 section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
102 section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
103 section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
105 for (i = 0; i < 512; i++) {
106 level2_table_0[i] = section_l2t0 | DEVICE_ATTR;
107 level2_table_1[i] = section_l2t1 | DEVICE_ATTR;
108 level2_table_2[i] = section_l2t2 | MEMORY_ATTR;
109 level2_table_3[i] = section_l2t3 | MEMORY_ATTR;
110 section_l2t0 += BLOCK_SIZE_L2;
111 section_l2t1 += BLOCK_SIZE_L2;
112 section_l2t2 += BLOCK_SIZE_L2;
113 section_l2t3 += BLOCK_SIZE_L2;
116 /* flush new MMU table */
117 flush_dcache_range(gd->arch.tlb_addr,
118 gd->arch.tlb_addr + gd->arch.tlb_size);
120 /* point TTBR to the new table */
122 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
123 TEGRA_TCR, MEMORY_ATTRIBUTES);
125 set_sctlr(get_sctlr() | CR_M);
128 u64 *arch_get_page_table(void)
130 return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));