2 * (C) Copyright 2010-2015
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clock.h>
12 #include <asm/arch/funcmux.h>
13 #include <asm/arch/mc.h>
14 #include <asm/arch/tegra.h>
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/board.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/sys_proto.h>
19 #include <asm/arch-tegra/warmboot.h>
21 void save_boot_params_ret(void);
23 DECLARE_GLOBAL_DATA_PTR;
26 /* UARTs which we can enable */
35 static bool from_spl __attribute__ ((section(".data")));
37 #ifndef CONFIG_SPL_BUILD
38 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
40 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
41 save_boot_params_ret();
45 bool spl_was_boot_source(void)
50 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
51 #if !defined(CONFIG_TEGRA124)
52 #error tegra_cpu_is_non_secure has only been validated on Tegra124
54 bool tegra_cpu_is_non_secure(void)
57 * This register reads 0xffffffff in non-secure mode. This register
58 * only implements bits 31:20, so the lower bits will always read 0 in
59 * secure mode. Thus, the lower bits are an indicator for secure vs.
62 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
63 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
64 return (mc_s_cfg0 & 1) == 1;
68 /* Read the RAM size directly from the memory controller */
69 static phys_size_t query_sdram_size(void)
71 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
73 phys_size_t size_bytes;
75 emem_cfg = readl(&mc->mc_emem_cfg);
76 #if defined(CONFIG_TEGRA20)
77 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
78 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
80 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
81 #ifndef CONFIG_PHYS_64BIT
83 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
84 * and will wrap. Clip the reported size to the maximum that a 32-bit
85 * variable can represent (rounded to a page).
87 if (emem_cfg >= 4096) {
88 size_bytes = U32_MAX & ~(0x1000 - 1);
92 /* RAM size EMC is programmed to. */
93 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
96 * If all RAM fits within 32-bits, it can be accessed without
97 * LPAE, so go test the RAM size. Otherwise, we can't access
98 * all the RAM, and get_ram_size() would get confused, so
99 * avoid using it. There's no reason we should need this
100 * validation step anyway.
102 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
103 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
109 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
110 /* External memory limited to 2047 MB due to IROM/HI-VEC */
111 if (size_bytes == SZ_2G)
120 /* We do not initialise DRAM here. We just query the size */
121 gd->ram_size = query_sdram_size();
125 static int uart_configs[] = {
126 #if defined(CONFIG_TEGRA20)
127 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
128 FUNCMUX_UART1_UAA_UAB,
129 #elif defined(CONFIG_TEGRA_UARTA_GPU)
131 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
134 FUNCMUX_UART1_IRRX_IRTX,
140 #elif defined(CONFIG_TEGRA30)
141 FUNCMUX_UART1_ULPI, /* UARTA */
146 #elif defined(CONFIG_TEGRA114)
150 FUNCMUX_UART4_GMI, /* UARTD */
152 #elif defined(CONFIG_TEGRA124)
153 FUNCMUX_UART1_KBC, /* UARTA */
156 FUNCMUX_UART4_GPIO, /* UARTD */
159 FUNCMUX_UART1_UART1, /* UARTA */
162 FUNCMUX_UART4_UART4, /* UARTD */
168 * Set up the specified uarts
170 * @param uarts_ids Mask containing UARTs to init (UARTx)
172 static void setup_uarts(int uart_ids)
174 static enum periph_id id_for_uart[] = {
183 for (i = 0; i < UART_COUNT; i++) {
184 if (uart_ids & (1 << i)) {
185 enum periph_id id = id_for_uart[i];
187 funcmux_select(id, uart_configs[i]);
188 clock_ll_start_uart(id);
193 void board_init_uart_f(void)
195 int uart_ids = 0; /* bit mask of which UART ids to enable */
197 #ifdef CONFIG_TEGRA_ENABLE_UARTA
200 #ifdef CONFIG_TEGRA_ENABLE_UARTB
203 #ifdef CONFIG_TEGRA_ENABLE_UARTC
206 #ifdef CONFIG_TEGRA_ENABLE_UARTD
209 #ifdef CONFIG_TEGRA_ENABLE_UARTE
212 setup_uarts(uart_ids);
215 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
216 void enable_caches(void)
218 /* Enable D-cache. I-cache is already enabled in start.S */