1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/funcmux.h>
14 #include <asm/arch/mc.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/ap.h>
17 #include <asm/arch-tegra/board.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/sys_proto.h>
20 #include <asm/arch-tegra/warmboot.h>
22 void save_boot_params_ret(void);
24 DECLARE_GLOBAL_DATA_PTR;
27 /* UARTs which we can enable */
36 static bool from_spl __attribute__ ((section(".data")));
38 #ifndef CONFIG_SPL_BUILD
39 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
41 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
42 save_boot_params_ret();
46 bool spl_was_boot_source(void)
51 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
52 #if !defined(CONFIG_TEGRA124)
53 #error tegra_cpu_is_non_secure has only been validated on Tegra124
55 bool tegra_cpu_is_non_secure(void)
58 * This register reads 0xffffffff in non-secure mode. This register
59 * only implements bits 31:20, so the lower bits will always read 0 in
60 * secure mode. Thus, the lower bits are an indicator for secure vs.
63 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
64 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
65 return (mc_s_cfg0 & 1) == 1;
69 /* Read the RAM size directly from the memory controller */
70 static phys_size_t query_sdram_size(void)
72 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
74 phys_size_t size_bytes;
76 emem_cfg = readl(&mc->mc_emem_cfg);
77 #if defined(CONFIG_TEGRA20)
78 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
79 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
81 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
82 #ifndef CONFIG_PHYS_64BIT
84 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
85 * and will wrap. Clip the reported size to the maximum that a 32-bit
86 * variable can represent (rounded to a page).
88 if (emem_cfg >= 4096) {
89 size_bytes = U32_MAX & ~(0x1000 - 1);
93 /* RAM size EMC is programmed to. */
94 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
97 * If all RAM fits within 32-bits, it can be accessed without
98 * LPAE, so go test the RAM size. Otherwise, we can't access
99 * all the RAM, and get_ram_size() would get confused, so
100 * avoid using it. There's no reason we should need this
101 * validation step anyway.
103 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
104 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
110 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
111 /* External memory limited to 2047 MB due to IROM/HI-VEC */
112 if (size_bytes == SZ_2G)
121 /* We do not initialise DRAM here. We just query the size */
122 gd->ram_size = query_sdram_size();
126 static int uart_configs[] = {
127 #if defined(CONFIG_TEGRA20)
128 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
129 FUNCMUX_UART1_UAA_UAB,
130 #elif defined(CONFIG_TEGRA_UARTA_GPU)
132 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
135 FUNCMUX_UART1_IRRX_IRTX,
141 #elif defined(CONFIG_TEGRA30)
142 FUNCMUX_UART1_ULPI, /* UARTA */
147 #elif defined(CONFIG_TEGRA114)
151 FUNCMUX_UART4_GMI, /* UARTD */
153 #elif defined(CONFIG_TEGRA124)
154 FUNCMUX_UART1_KBC, /* UARTA */
157 FUNCMUX_UART4_GPIO, /* UARTD */
160 FUNCMUX_UART1_UART1, /* UARTA */
163 FUNCMUX_UART4_UART4, /* UARTD */
169 * Set up the specified uarts
171 * @param uarts_ids Mask containing UARTs to init (UARTx)
173 static void setup_uarts(int uart_ids)
175 static enum periph_id id_for_uart[] = {
184 for (i = 0; i < UART_COUNT; i++) {
185 if (uart_ids & (1 << i)) {
186 enum periph_id id = id_for_uart[i];
188 funcmux_select(id, uart_configs[i]);
189 clock_ll_start_uart(id);
194 void board_init_uart_f(void)
196 int uart_ids = 0; /* bit mask of which UART ids to enable */
198 #ifdef CONFIG_TEGRA_ENABLE_UARTA
201 #ifdef CONFIG_TEGRA_ENABLE_UARTB
204 #ifdef CONFIG_TEGRA_ENABLE_UARTC
207 #ifdef CONFIG_TEGRA_ENABLE_UARTD
210 #ifdef CONFIG_TEGRA_ENABLE_UARTE
213 setup_uarts(uart_ids);
216 #if !CONFIG_IS_ENABLED(OF_CONTROL)
217 static struct ns16550_platdata ns16550_com1_pdata = {
218 .base = CONFIG_SYS_NS16550_COM1,
220 .clock = CONFIG_SYS_NS16550_CLK,
221 .fcr = UART_FCR_DEFVAL,
224 U_BOOT_DEVICE(ns16550_com1) = {
225 "ns16550_serial", &ns16550_com1_pdata
229 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
230 void enable_caches(void)
232 /* Enable D-cache. I-cache is already enabled in start.S */