2 * (C) Copyright 2010-2014
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/funcmux.h>
12 #include <asm/arch/mc.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/board.h>
15 #include <asm/arch-tegra/pmc.h>
16 #include <asm/arch-tegra/sys_proto.h>
17 #include <asm/arch-tegra/warmboot.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 /* UARTs which we can enable */
31 /* Read the RAM size directly from the memory controller */
32 unsigned int query_sdram_size(void)
34 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
35 u32 emem_cfg, size_bytes;
37 emem_cfg = readl(&mc->mc_emem_cfg);
38 #if defined(CONFIG_TEGRA20)
39 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
40 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
42 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
44 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
45 * and will wrap. Clip the reported size to the maximum that a 32-bit
46 * variable can represent (rounded to a page).
48 if (emem_cfg >= 4096) {
49 size_bytes = U32_MAX & ~(0x1000 - 1);
51 /* RAM size EMC is programmed to. */
52 size_bytes = emem_cfg * 1024 * 1024;
54 * If all RAM fits within 32-bits, it can be accessed without
55 * LPAE, so go test the RAM size. Otherwise, we can't access
56 * all the RAM, and get_ram_size() would get confused, so
57 * avoid using it. There's no reason we should need this
58 * validation step anyway.
60 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
61 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
66 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
67 /* External memory limited to 2047 MB due to IROM/HI-VEC */
68 if (size_bytes == SZ_2G)
77 /* We do not initialise DRAM here. We just query the size */
78 gd->ram_size = query_sdram_size();
82 #ifdef CONFIG_DISPLAY_BOARDINFO
85 printf("Board: %s\n", sysinfo.board_string);
88 #endif /* CONFIG_DISPLAY_BOARDINFO */
90 static int uart_configs[] = {
91 #if defined(CONFIG_TEGRA20)
92 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
93 FUNCMUX_UART1_UAA_UAB,
94 #elif defined(CONFIG_TEGRA_UARTA_GPU)
96 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
99 FUNCMUX_UART1_IRRX_IRTX,
105 #elif defined(CONFIG_TEGRA30)
106 FUNCMUX_UART1_ULPI, /* UARTA */
111 #elif defined(CONFIG_TEGRA114)
115 FUNCMUX_UART4_GMI, /* UARTD */
118 FUNCMUX_UART1_KBC, /* UARTA */
121 FUNCMUX_UART4_GPIO, /* UARTD */
127 * Set up the specified uarts
129 * @param uarts_ids Mask containing UARTs to init (UARTx)
131 static void setup_uarts(int uart_ids)
133 static enum periph_id id_for_uart[] = {
142 for (i = 0; i < UART_COUNT; i++) {
143 if (uart_ids & (1 << i)) {
144 enum periph_id id = id_for_uart[i];
146 funcmux_select(id, uart_configs[i]);
147 clock_ll_start_uart(id);
152 void board_init_uart_f(void)
154 int uart_ids = 0; /* bit mask of which UART ids to enable */
156 #ifdef CONFIG_TEGRA_ENABLE_UARTA
159 #ifdef CONFIG_TEGRA_ENABLE_UARTB
162 #ifdef CONFIG_TEGRA_ENABLE_UARTC
165 #ifdef CONFIG_TEGRA_ENABLE_UARTD
168 #ifdef CONFIG_TEGRA_ENABLE_UARTE
171 setup_uarts(uart_ids);
174 #ifndef CONFIG_SYS_DCACHE_OFF
175 void enable_caches(void)
177 /* Enable D-cache. I-cache is already enabled in start.S */