2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/board.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/sys_proto.h>
19 #include <asm/arch-tegra/uart.h>
20 #include <asm/arch-tegra/warmboot.h>
21 #include <asm/arch-tegra/gpu.h>
22 #include <asm/arch-tegra/usb.h>
23 #include <asm/arch-tegra/xusb-padctl.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/funcmux.h>
26 #include <asm/arch/pinmux.h>
27 #include <asm/arch/pmu.h>
28 #include <asm/arch/tegra.h>
29 #ifdef CONFIG_TEGRA_CLOCK_SCALING
30 #include <asm/arch/emc.h>
32 #include <power/as3722.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #ifdef CONFIG_SPL_BUILD
38 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
39 U_BOOT_DEVICE(tegra_gpios) = {
44 __weak void pinmux_init(void) {}
45 __weak void pin_mux_usb(void) {}
46 __weak void pin_mux_spi(void) {}
47 __weak void pin_mux_mmc(void) {}
48 __weak void gpio_early_init_uart(void) {}
49 __weak void pin_mux_display(void) {}
50 __weak void start_cpu_fan(void) {}
52 #if defined(CONFIG_TEGRA_NAND)
53 __weak void pin_mux_nand(void)
55 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
60 * Routine: power_det_init
61 * Description: turn off power detects
63 static void power_det_init(void)
65 #if defined(CONFIG_TEGRA20)
66 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
68 /* turn off power detects */
69 writel(0, &pmc->pmc_pwr_det_latch);
70 writel(0, &pmc->pmc_pwr_det);
74 __weak int tegra_board_id(void)
79 #ifdef CONFIG_DISPLAY_BOARDINFO
82 int board_id = tegra_board_id();
84 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
86 printf(", ID: %d\n", board_id);
91 #endif /* CONFIG_DISPLAY_BOARDINFO */
93 __weak int tegra_lcd_pmic_init(int board_it)
98 __weak int nvidia_board_init(void)
104 * Routine: board_init
105 * Description: Early hardware init.
109 __maybe_unused int err;
110 __maybe_unused int board_id;
112 /* Do clocks and UART first so that printf() works */
118 #ifdef CONFIG_TEGRA_SPI
122 #ifdef CONFIG_MMC_SDHCI_TEGRA
126 /* Init is handled automatically in the driver-model case */
127 #if defined(CONFIG_DM_VIDEO)
130 /* boot param addr */
131 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
135 #ifdef CONFIG_SYS_I2C_TEGRA
136 # ifdef CONFIG_TEGRA_PMU
137 if (pmu_set_nominal())
138 debug("Failed to select nominal voltages\n");
139 # ifdef CONFIG_TEGRA_CLOCK_SCALING
140 err = board_emc_init();
142 debug("Memory controller init failed: %d\n", err);
144 # endif /* CONFIG_TEGRA_PMU */
145 #ifdef CONFIG_PMIC_AS3722
146 err = as3722_init(NULL);
147 if (err && err != -ENODEV)
150 #endif /* CONFIG_SYS_I2C_TEGRA */
152 #ifdef CONFIG_USB_EHCI_TEGRA
156 #if defined(CONFIG_DM_VIDEO)
157 board_id = tegra_board_id();
158 err = tegra_lcd_pmic_init(board_id);
163 #ifdef CONFIG_TEGRA_NAND
167 tegra_xusb_padctl_init(gd->fdt_blob);
169 #ifdef CONFIG_TEGRA_LP0
170 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
171 warmboot_save_sdram_params();
173 /* prepare the WB code to LP0 location */
174 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
176 return nvidia_board_init();
179 #ifdef CONFIG_BOARD_EARLY_INIT_F
180 static void __gpio_early_init(void)
184 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
186 int board_early_init_f(void)
188 if (!clock_early_init_done())
191 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
192 #define USBCMD_FS2 (1 << 15)
194 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
195 writel(USBCMD_FS2, &usbctlr->usb_cmd);
199 /* Do any special system timer/TSC setup */
200 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
201 if (!tegra_cpu_is_non_secure())
208 /* Initialize periph GPIOs */
210 gpio_early_init_uart();
214 #endif /* EARLY_INIT */
216 int board_late_init(void)
218 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
219 if (tegra_cpu_is_non_secure()) {
220 printf("CPU is in NS mode\n");
221 setenv("cpu_ns_mode", "1");
223 setenv("cpu_ns_mode", "");
232 * In some SW environments, a memory carve-out exists to house a secure
233 * monitor, a trusted OS, and/or various statically allocated media buffers.
235 * This carveout exists at the highest possible address that is within a
236 * 32-bit physical address space.
238 * This function returns the total size of this carve-out. At present, the
239 * returned value is hard-coded for simplicity. In the future, it may be
240 * possible to determine the carve-out size:
241 * - By querying some run-time information source, such as:
242 * - A structure passed to U-Boot by earlier boot software.
244 * - A call into the secure monitor.
245 * - In the per-board U-Boot configuration header, based on knowledge of the
246 * SW environment that U-Boot is being built for.
248 * For now, we support two configurations in U-Boot:
249 * - 32-bit ports without any form of carve-out.
250 * - 64 bit ports which are assumed to use a carve-out of a conservatively
253 static ulong carveout_size(void)
263 * Determine the amount of usable RAM below 4GiB, taking into account any
264 * carve-out that may be assigned.
266 static ulong usable_ram_size_below_4g(void)
268 ulong total_size_below_4g;
269 ulong usable_size_below_4g;
272 * The total size of RAM below 4GiB is the lesser address of:
273 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
274 * (b) The size RAM physically present in the system.
276 if (gd->ram_size < SZ_2G)
277 total_size_below_4g = gd->ram_size;
279 total_size_below_4g = SZ_2G;
281 /* Calculate usable RAM by subtracting out any carve-out size */
282 usable_size_below_4g = total_size_below_4g - carveout_size();
284 return usable_size_below_4g;
288 * Represent all available RAM in either one or two banks.
290 * The first bank describes any usable RAM below 4GiB.
291 * The second bank describes any RAM above 4GiB.
293 * This split is driven by the following requirements:
294 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
295 * property for memory below and above the 4GiB boundary. The layout of that
296 * DT property is directly driven by the entries in the U-Boot bank array.
297 * - The potential existence of a carve-out at the end of RAM below 4GiB can
298 * only be represented using multiple banks.
300 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
301 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
304 * This does mean that the DT U-Boot passes to the Linux kernel will not
305 * include this RAM in /memory/reg at all. An alternative would be to include
306 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
307 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
308 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
309 * mapping, so either way is acceptable.
311 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
312 * start address of that bank cannot be represented in the 32-bit .size
315 int dram_init_banksize(void)
317 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
318 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
321 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
324 #ifdef CONFIG_PHYS_64BIT
325 if (gd->ram_size > SZ_2G) {
326 gd->bd->bi_dram[1].start = 0x100000000;
327 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
331 gd->bd->bi_dram[1].start = 0;
332 gd->bd->bi_dram[1].size = 0;
339 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
340 * 32-bits of the physical address space. Cap the maximum usable RAM area
341 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
342 * boundary that most devices can address. Also, don't let U-Boot use any
343 * carve-out, as mentioned above.
345 * This function is called before dram_init_banksize(), so we can't simply
346 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
348 ulong board_get_usable_ram_top(ulong total_size)
350 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();