2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
13 #include <linux/sizes.h>
15 #include <asm/arch/clock.h>
17 #include <asm/arch/display.h>
19 #include <asm/arch/funcmux.h>
20 #include <asm/arch/pinmux.h>
21 #include <asm/arch/pmu.h>
22 #ifdef CONFIG_PWM_TEGRA
23 #include <asm/arch/pwm.h>
25 #include <asm/arch/tegra.h>
26 #include <asm/arch-tegra/ap.h>
27 #include <asm/arch-tegra/board.h>
28 #include <asm/arch-tegra/clk_rst.h>
29 #include <asm/arch-tegra/pmc.h>
30 #include <asm/arch-tegra/sys_proto.h>
31 #include <asm/arch-tegra/uart.h>
32 #include <asm/arch-tegra/warmboot.h>
33 #include <asm/arch-tegra/gpu.h>
34 #ifdef CONFIG_TEGRA_CLOCK_SCALING
35 #include <asm/arch/emc.h>
37 #include <asm/arch-tegra/usb.h>
38 #ifdef CONFIG_USB_EHCI_TEGRA
41 #ifdef CONFIG_TEGRA_MMC
42 #include <asm/arch-tegra/tegra_mmc.h>
43 #include <asm/arch-tegra/mmc.h>
45 #include <asm/arch-tegra/xusb-padctl.h>
46 #include <power/as3722.h>
51 DECLARE_GLOBAL_DATA_PTR;
53 #ifdef CONFIG_SPL_BUILD
54 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
55 U_BOOT_DEVICE(tegra_gpios) = {
60 __weak void pinmux_init(void) {}
61 __weak void pin_mux_usb(void) {}
62 __weak void pin_mux_spi(void) {}
63 __weak void gpio_early_init_uart(void) {}
64 __weak void pin_mux_display(void) {}
65 __weak void start_cpu_fan(void) {}
67 #if defined(CONFIG_TEGRA_NAND)
68 __weak void pin_mux_nand(void)
70 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
75 * Routine: power_det_init
76 * Description: turn off power detects
78 static void power_det_init(void)
80 #if defined(CONFIG_TEGRA20)
81 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
83 /* turn off power detects */
84 writel(0, &pmc->pmc_pwr_det_latch);
85 writel(0, &pmc->pmc_pwr_det);
89 __weak int tegra_board_id(void)
94 #ifdef CONFIG_DISPLAY_BOARDINFO
97 int board_id = tegra_board_id();
99 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
101 printf(", ID: %d\n", board_id);
106 #endif /* CONFIG_DISPLAY_BOARDINFO */
108 __weak int tegra_lcd_pmic_init(int board_it)
113 __weak int nvidia_board_init(void)
119 * Routine: board_init
120 * Description: Early hardware init.
124 __maybe_unused int err;
125 __maybe_unused int board_id;
127 /* Do clocks and UART first so that printf() works */
133 #ifdef CONFIG_TEGRA_SPI
137 /* Init is handled automatically in the driver-model case */
138 #if defined(CONFIG_PWM_TEGRA) && !defined(CONFIG_PWM)
139 if (pwm_init(gd->fdt_blob))
140 debug("%s: Failed to init pwm\n", __func__);
144 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
146 /* boot param addr */
147 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
151 #ifdef CONFIG_SYS_I2C_TEGRA
152 # ifdef CONFIG_TEGRA_PMU
153 if (pmu_set_nominal())
154 debug("Failed to select nominal voltages\n");
155 # ifdef CONFIG_TEGRA_CLOCK_SCALING
156 err = board_emc_init();
158 debug("Memory controller init failed: %d\n", err);
160 # endif /* CONFIG_TEGRA_PMU */
161 #ifdef CONFIG_AS3722_POWER
162 err = as3722_init(NULL);
163 if (err && err != -ENODEV)
166 #endif /* CONFIG_SYS_I2C_TEGRA */
168 #ifdef CONFIG_USB_EHCI_TEGRA
173 board_id = tegra_board_id();
174 err = tegra_lcd_pmic_init(board_id);
177 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
180 #ifdef CONFIG_TEGRA_NAND
184 tegra_xusb_padctl_init(gd->fdt_blob);
186 #ifdef CONFIG_TEGRA_LP0
187 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
188 warmboot_save_sdram_params();
190 /* prepare the WB code to LP0 location */
191 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
193 return nvidia_board_init();
196 #ifdef CONFIG_BOARD_EARLY_INIT_F
197 static void __gpio_early_init(void)
201 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
203 int board_early_init_f(void)
205 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
206 #define USBCMD_FS2 (1 << 15)
208 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
209 writel(USBCMD_FS2, &usbctlr->usb_cmd);
213 /* Do any special system timer/TSC setup */
214 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
215 if (!tegra_cpu_is_non_secure())
222 /* Initialize periph GPIOs */
224 gpio_early_init_uart();
226 tegra_lcd_early_init(gd->fdt_blob);
231 #endif /* EARLY_INIT */
233 int board_late_init(void)
236 /* Make sure we finish initing the LCD */
237 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
239 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
240 if (tegra_cpu_is_non_secure()) {
241 printf("CPU is in NS mode\n");
242 setenv("cpu_ns_mode", "1");
244 setenv("cpu_ns_mode", "");
252 #if defined(CONFIG_TEGRA_MMC)
253 __weak void pin_mux_mmc(void)
257 /* this is a weak define that we are overriding */
258 int board_mmc_init(bd_t *bd)
260 debug("%s called\n", __func__);
262 /* Enable muxes, etc. for SDMMC controllers */
265 debug("%s: init MMC\n", __func__);
271 void pad_init_mmc(struct mmc_host *host)
273 #if defined(CONFIG_TEGRA30)
274 enum periph_id id = host->mmc_id;
277 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
278 (unsigned int)host->reg, id);
280 /* Set the pad drive strength for SDMMC1 or 3 only */
281 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
282 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
287 val = readl(&host->reg->sdmemcmppadctl);
289 val |= MEMCOMP_PADCTRL_VREF;
290 writel(val, &host->reg->sdmemcmppadctl);
292 val = readl(&host->reg->autocalcfg);
294 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
295 writel(val, &host->reg->autocalcfg);
301 * In some SW environments, a memory carve-out exists to house a secure
302 * monitor, a trusted OS, and/or various statically allocated media buffers.
304 * This carveout exists at the highest possible address that is within a
305 * 32-bit physical address space.
307 * This function returns the total size of this carve-out. At present, the
308 * returned value is hard-coded for simplicity. In the future, it may be
309 * possible to determine the carve-out size:
310 * - By querying some run-time information source, such as:
311 * - A structure passed to U-Boot by earlier boot software.
313 * - A call into the secure monitor.
314 * - In the per-board U-Boot configuration header, based on knowledge of the
315 * SW environment that U-Boot is being built for.
317 * For now, we support two configurations in U-Boot:
318 * - 32-bit ports without any form of carve-out.
319 * - 64 bit ports which are assumed to use a carve-out of a conservatively
322 static ulong carveout_size(void)
332 * Determine the amount of usable RAM below 4GiB, taking into account any
333 * carve-out that may be assigned.
335 static ulong usable_ram_size_below_4g(void)
337 ulong total_size_below_4g;
338 ulong usable_size_below_4g;
341 * The total size of RAM below 4GiB is the lesser address of:
342 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
343 * (b) The size RAM physically present in the system.
345 if (gd->ram_size < SZ_2G)
346 total_size_below_4g = gd->ram_size;
348 total_size_below_4g = SZ_2G;
350 /* Calculate usable RAM by subtracting out any carve-out size */
351 usable_size_below_4g = total_size_below_4g - carveout_size();
353 return usable_size_below_4g;
357 * Represent all available RAM in either one or two banks.
359 * The first bank describes any usable RAM below 4GiB.
360 * The second bank describes any RAM above 4GiB.
362 * This split is driven by the following requirements:
363 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
364 * property for memory below and above the 4GiB boundary. The layout of that
365 * DT property is directly driven by the entries in the U-Boot bank array.
366 * - The potential existence of a carve-out at the end of RAM below 4GiB can
367 * only be represented using multiple banks.
369 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
370 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
373 * This does mean that the DT U-Boot passes to the Linux kernel will not
374 * include this RAM in /memory/reg at all. An alternative would be to include
375 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
376 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
377 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
378 * mapping, so either way is acceptable.
380 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
381 * start address of that bank cannot be represented in the 32-bit .size
384 void dram_init_banksize(void)
386 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
387 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
390 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
393 #ifdef CONFIG_PHYS_64BIT
394 if (gd->ram_size > SZ_2G) {
395 gd->bd->bi_dram[1].start = 0x100000000;
396 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
400 gd->bd->bi_dram[1].start = 0;
401 gd->bd->bi_dram[1].size = 0;
406 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
407 * 32-bits of the physical address space. Cap the maximum usable RAM area
408 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
409 * boundary that most devices can address. Also, don't let U-Boot use any
410 * carve-out, as mentioned above.
412 * This function is called before dram_init_banksize(), so we can't simply
413 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
415 ulong board_get_usable_ram_top(ulong total_size)
417 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();
421 * This function is called right before the kernel is booted. "blob" is the
422 * device tree that will be passed to the kernel.
424 int ft_system_setup(void *blob, bd_t *bd)
426 const char *gpu_path =
427 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
433 /* Enable GPU node if GPU setup has been performed */
434 if (gpu_path != NULL)
435 return tegra_gpu_enable_node(blob, gpu_path);