2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
14 #include <asm/arch/clock.h>
16 #include <asm/arch/display.h>
18 #include <asm/arch/funcmux.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/pmu.h>
21 #ifdef CONFIG_PWM_TEGRA
22 #include <asm/arch/pwm.h>
24 #include <asm/arch/tegra.h>
25 #include <asm/arch-tegra/ap.h>
26 #include <asm/arch-tegra/board.h>
27 #include <asm/arch-tegra/clk_rst.h>
28 #include <asm/arch-tegra/pmc.h>
29 #include <asm/arch-tegra/sys_proto.h>
30 #include <asm/arch-tegra/uart.h>
31 #include <asm/arch-tegra/warmboot.h>
32 #include <asm/arch-tegra/gpu.h>
33 #ifdef CONFIG_TEGRA_CLOCK_SCALING
34 #include <asm/arch/emc.h>
36 #ifdef CONFIG_USB_EHCI_TEGRA
37 #include <asm/arch-tegra/usb.h>
40 #ifdef CONFIG_TEGRA_MMC
41 #include <asm/arch-tegra/tegra_mmc.h>
42 #include <asm/arch-tegra/mmc.h>
44 #include <asm/arch-tegra/xusb-padctl.h>
45 #include <power/as3722.h>
50 DECLARE_GLOBAL_DATA_PTR;
52 #ifdef CONFIG_SPL_BUILD
53 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
54 U_BOOT_DEVICE(tegra_gpios) = {
59 __weak void pinmux_init(void) {}
60 __weak void pin_mux_usb(void) {}
61 __weak void pin_mux_spi(void) {}
62 __weak void gpio_early_init_uart(void) {}
63 __weak void pin_mux_display(void) {}
64 __weak void start_cpu_fan(void) {}
66 #if defined(CONFIG_TEGRA_NAND)
67 __weak void pin_mux_nand(void)
69 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
74 * Routine: power_det_init
75 * Description: turn off power detects
77 static void power_det_init(void)
79 #if defined(CONFIG_TEGRA20)
80 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
82 /* turn off power detects */
83 writel(0, &pmc->pmc_pwr_det_latch);
84 writel(0, &pmc->pmc_pwr_det);
88 __weak int tegra_board_id(void)
93 #ifdef CONFIG_DISPLAY_BOARDINFO
96 int board_id = tegra_board_id();
98 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
100 printf(", ID: %d\n", board_id);
105 #endif /* CONFIG_DISPLAY_BOARDINFO */
107 __weak int tegra_lcd_pmic_init(int board_it)
112 __weak int nvidia_board_init(void)
118 * Routine: board_init
119 * Description: Early hardware init.
123 __maybe_unused int err;
124 __maybe_unused int board_id;
126 /* Do clocks and UART first so that printf() works */
132 #ifdef CONFIG_TEGRA_SPI
136 #ifdef CONFIG_PWM_TEGRA
137 if (pwm_init(gd->fdt_blob))
138 debug("%s: Failed to init pwm\n", __func__);
142 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
144 /* boot param addr */
145 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
149 #ifdef CONFIG_SYS_I2C_TEGRA
150 # ifdef CONFIG_TEGRA_PMU
151 if (pmu_set_nominal())
152 debug("Failed to select nominal voltages\n");
153 # ifdef CONFIG_TEGRA_CLOCK_SCALING
154 err = board_emc_init();
156 debug("Memory controller init failed: %d\n", err);
158 # endif /* CONFIG_TEGRA_PMU */
159 #ifdef CONFIG_AS3722_POWER
160 err = as3722_init(NULL);
161 if (err && err != -ENODEV)
164 #endif /* CONFIG_SYS_I2C_TEGRA */
166 #ifdef CONFIG_USB_EHCI_TEGRA
171 board_id = tegra_board_id();
172 err = tegra_lcd_pmic_init(board_id);
175 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
178 #ifdef CONFIG_TEGRA_NAND
182 tegra_xusb_padctl_init(gd->fdt_blob);
184 #ifdef CONFIG_TEGRA_LP0
185 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
186 warmboot_save_sdram_params();
188 /* prepare the WB code to LP0 location */
189 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
191 return nvidia_board_init();
194 #ifdef CONFIG_BOARD_EARLY_INIT_F
195 static void __gpio_early_init(void)
199 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
201 int board_early_init_f(void)
203 /* Do any special system timer/TSC setup */
204 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
205 if (!tegra_cpu_is_non_secure())
212 /* Initialize periph GPIOs */
214 gpio_early_init_uart();
216 tegra_lcd_early_init(gd->fdt_blob);
221 #endif /* EARLY_INIT */
223 int board_late_init(void)
226 /* Make sure we finish initing the LCD */
227 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
229 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
230 if (tegra_cpu_is_non_secure()) {
231 printf("CPU is in NS mode\n");
232 setenv("cpu_ns_mode", "1");
234 setenv("cpu_ns_mode", "");
242 #if defined(CONFIG_TEGRA_MMC)
243 __weak void pin_mux_mmc(void)
247 /* this is a weak define that we are overriding */
248 int board_mmc_init(bd_t *bd)
250 debug("%s called\n", __func__);
252 /* Enable muxes, etc. for SDMMC controllers */
255 debug("%s: init MMC\n", __func__);
261 void pad_init_mmc(struct mmc_host *host)
263 #if defined(CONFIG_TEGRA30)
264 enum periph_id id = host->mmc_id;
267 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
268 (unsigned int)host->reg, id);
270 /* Set the pad drive strength for SDMMC1 or 3 only */
271 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
272 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
277 val = readl(&host->reg->sdmemcmppadctl);
279 val |= MEMCOMP_PADCTRL_VREF;
280 writel(val, &host->reg->sdmemcmppadctl);
282 val = readl(&host->reg->autocalcfg);
284 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
285 writel(val, &host->reg->autocalcfg);
292 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
293 * 32-bits of the physical address space. Cap the maximum usable RAM area
294 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
295 * boundary that most devices can address.
297 * Additionally, ARM64 devices typically run a secure monitor in EL3 and
298 * U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3
299 * code and data. These carve-outs are located at the top of 32-bit address
300 * space. Restrict U-Boot's RAM usage to well below the location of those
301 * carve-outs. Ideally, we would the secure monitor would inform U-Boot of
302 * exactly which RAM it could use at run-time. However, I'm not sure how to
303 * do that at present (and even if such a mechanism does exist, it would
304 * likely not be generic across all forms of secure monitor).
306 ulong board_get_usable_ram_top(ulong total_size)
308 if (gd->ram_top > 0xe0000000)