2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 /* Tegra SoC common clock control functions */
12 #include <asm/arch/clock.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/timer.h>
22 * This is our record of the current clock rate of each clock. We don't
23 * fill all of these in since we are only really interested in clocks which
26 static unsigned pll_rate[CLOCK_ID_COUNT];
29 * The oscillator frequency is fixed to one of four set values. Based on this
30 * the other clocks are set up appropriately.
32 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
41 /* return 1 if a peripheral ID is in range */
42 #define clock_type_id_isvalid(id) ((id) >= 0 && \
43 (id) < CLOCK_TYPE_COUNT)
45 char pllp_valid = 1; /* PLLP is set up correctly */
47 /* return 1 if a periphc_internal_id is in range */
48 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
51 /* number of clock outputs of a PLL */
52 static const u8 pll_num_clkouts[] = {
61 int clock_get_osc_bypass(void)
63 struct clk_rst_ctlr *clkrst =
64 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
67 reg = readl(&clkrst->crc_osc_ctrl);
68 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
71 /* Returns a pointer to the registers of the given pll */
72 static struct clk_pll *get_pll(enum clock_id clkid)
74 struct clk_rst_ctlr *clkrst =
75 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
77 assert(clock_id_is_pll(clkid));
78 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
79 debug("%s: Invalid PLL %d\n", __func__, clkid);
82 return &clkrst->crc_pll[clkid];
85 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
91 u32 *divp, u32 *cpcon, u32 *lfcon)
93 struct clk_pll *pll = get_pll(clkid);
94 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
97 assert(clkid != CLOCK_ID_USB);
99 /* Safety check, adds to code size but is small */
100 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
102 data = readl(&pll->pll_base);
103 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
105 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
106 data = readl(&pll->pll_misc);
107 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
108 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
109 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
114 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
115 u32 divp, u32 cpcon, u32 lfcon)
117 struct clk_pll *pll = NULL;
118 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
119 struct clk_pll_simple *simple_pll = NULL;
122 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
123 pll = get_pll(clkid);
125 simple_pll = clock_get_simple_pll(clkid);
127 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
133 * pllinfo has the m/n/p and kcp/kvco mask and shift
134 * values for all of the PLLs used in U-Boot, with any
135 * SoC differences accounted for.
137 * Preserve EN_LOCKDET, etc.
140 misc_data = readl(&pll->pll_misc);
142 misc_data = readl(&simple_pll->pll_misc);
143 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
144 misc_data |= cpcon << pllinfo->kcp_shift;
145 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
146 misc_data |= lfcon << pllinfo->kvco_shift;
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
149 data |= divp << pllinfo->p_shift;
150 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
153 writel(misc_data, &pll->pll_misc);
154 writel(data, &pll->pll_base);
156 writel(misc_data, &simple_pll->pll_misc);
157 writel(data, &simple_pll->pll_base);
160 /* calculate the stable time */
161 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
164 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
167 u32 *reg = get_periph_source_reg(periph_id);
172 value &= ~OUT_CLK_SOURCE_31_30_MASK;
173 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
175 value &= ~OUT_CLK_DIVISOR_MASK;
176 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
181 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
184 u32 *reg = get_periph_source_reg(periph_id);
187 case MASK_BITS_31_30:
188 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
189 source << OUT_CLK_SOURCE_31_30_SHIFT);
192 case MASK_BITS_31_29:
193 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
194 source << OUT_CLK_SOURCE_31_29_SHIFT);
197 case MASK_BITS_31_28:
198 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
199 source << OUT_CLK_SOURCE_31_28_SHIFT);
209 static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
211 u32 *reg = get_periph_source_reg(periph_id);
212 u32 val = readl(reg);
215 case MASK_BITS_31_30:
216 val >>= OUT_CLK_SOURCE_31_30_SHIFT;
217 val &= OUT_CLK_SOURCE_31_30_MASK;
219 case MASK_BITS_31_29:
220 val >>= OUT_CLK_SOURCE_31_29_SHIFT;
221 val &= OUT_CLK_SOURCE_31_29_MASK;
223 case MASK_BITS_31_28:
224 val >>= OUT_CLK_SOURCE_31_28_SHIFT;
225 val &= OUT_CLK_SOURCE_31_28_MASK;
232 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
234 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
238 * Given the parent's rate and the required rate for the children, this works
239 * out the peripheral clock divider to use, in 7.1 binary format.
241 * @param divider_bits number of divider bits (8 or 16)
242 * @param parent_rate clock rate of parent clock in Hz
243 * @param rate required clock rate for this clock
244 * @return divider which should be used
246 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
249 u64 divider = parent_rate * 2;
250 unsigned max_divider = 1 << divider_bits;
253 do_div(divider, rate);
255 if ((s64)divider - 2 < 0)
258 if ((s64)divider - 2 >= max_divider)
264 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
266 struct clk_pll *pll = get_pll(clkid);
267 int data = 0, div = 0, offset = 0;
269 if (!clock_id_is_pll(clkid))
272 if (pllout + 1 > pll_num_clkouts[clkid])
275 div = clk_get_divider(8, pll_rate[clkid], rate);
280 /* out2 and out4 are in the high part of the register */
281 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
284 data = (div << PLL_OUT_RATIO_SHIFT) |
285 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
286 clrsetbits_le32(&pll->pll_out[pllout >> 1],
287 PLL_OUT_RATIO_MASK << offset, data << offset);
293 * Given the parent's rate and the divider in 7.1 format, this works out the
294 * resulting peripheral clock rate.
296 * @param parent_rate clock rate of parent clock in Hz
297 * @param divider which should be used in 7.1 format
298 * @return effective clock rate of peripheral
300 static unsigned long get_rate_from_divider(unsigned long parent_rate,
305 rate = (u64)parent_rate * 2;
306 do_div(rate, divider + 2);
310 unsigned long clock_get_periph_rate(enum periph_id periph_id,
311 enum clock_id parent)
313 u32 *reg = get_periph_source_reg(periph_id);
315 return get_rate_from_divider(pll_rate[parent],
316 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
320 * Find the best available 7.1 format divisor given a parent clock rate and
321 * required child clock rate. This function assumes that a second-stage
322 * divisor is available which can divide by powers of 2 from 1 to 256.
324 * @param divider_bits number of divider bits (8 or 16)
325 * @param parent_rate clock rate of parent clock in Hz
326 * @param rate required clock rate for this clock
327 * @param extra_div value for the second-stage divisor (not set if this
328 * function returns -1.
329 * @return divider which should be used, or -1 if nothing is valid
332 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
333 unsigned long rate, int *extra_div)
336 int best_divider = -1;
337 int best_error = rate;
339 /* try dividers from 1 to 256 and find closest match */
340 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
341 unsigned divided_parent = parent_rate >> shift;
342 int divider = clk_get_divider(divider_bits, divided_parent,
344 unsigned effective_rate = get_rate_from_divider(divided_parent,
346 int error = rate - effective_rate;
348 /* Given a valid divider, look for the lowest error */
349 if (divider != -1 && error < best_error) {
351 *extra_div = 1 << shift;
352 best_divider = divider;
356 /* return what we found - *extra_div will already be set */
361 * Adjust peripheral PLL to use the given divider and source.
363 * @param periph_id peripheral to adjust
364 * @param source Source number (0-3 or 0-7)
365 * @param mux_bits Number of mux bits (2 or 4)
366 * @param divider Required divider in 7.1 or 15.1 format
367 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
368 * for this peripheral)
370 static int adjust_periph_pll(enum periph_id periph_id, int source,
371 int mux_bits, unsigned divider)
373 u32 *reg = get_periph_source_reg(periph_id);
375 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
376 divider << OUT_CLK_DIVISOR_SHIFT);
379 /* work out the source clock and set it */
383 clock_ll_set_source_bits(periph_id, mux_bits, source);
389 enum clock_id clock_get_periph_parent(enum periph_id periph_id)
391 int err, mux_bits, divider_bits, type;
394 err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type);
396 return CLOCK_ID_NONE;
398 source = clock_ll_get_source_bits(periph_id, mux_bits);
400 return get_periph_clock_id(periph_id, source);
403 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
404 enum clock_id parent, unsigned rate, int *extra_div)
406 unsigned effective_rate;
407 int mux_bits, divider_bits, source;
411 /* work out the source clock and set it */
412 source = get_periph_clock_source(periph_id, parent, &mux_bits,
415 divider = find_best_divider(divider_bits, pll_rate[parent],
420 assert(divider >= 0);
421 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
423 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
424 get_periph_source_reg(periph_id),
425 readl(get_periph_source_reg(periph_id)));
427 /* Check what we ended up with. This shouldn't matter though */
428 effective_rate = clock_get_periph_rate(periph_id, parent);
430 effective_rate /= *extra_div;
431 if (rate != effective_rate)
432 debug("Requested clock rate %u not honored (got %u)\n",
433 rate, effective_rate);
434 return effective_rate;
437 unsigned clock_start_periph_pll(enum periph_id periph_id,
438 enum clock_id parent, unsigned rate)
440 unsigned effective_rate;
442 reset_set_enable(periph_id, 1);
443 clock_enable(periph_id);
445 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
448 reset_set_enable(periph_id, 0);
449 return effective_rate;
452 void clock_enable(enum periph_id clkid)
454 clock_set_enable(clkid, 1);
457 void clock_disable(enum periph_id clkid)
459 clock_set_enable(clkid, 0);
462 void reset_periph(enum periph_id periph_id, int us_delay)
464 /* Put peripheral into reset */
465 reset_set_enable(periph_id, 1);
469 reset_set_enable(periph_id, 0);
474 void reset_cmplx_set_enable(int cpu, int which, int reset)
476 struct clk_rst_ctlr *clkrst =
477 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
480 /* Form the mask, which depends on the cpu chosen (2 or 4) */
481 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
484 /* either enable or disable those reset for that CPU */
486 writel(mask, &clkrst->crc_cpu_cmplx_set);
488 writel(mask, &clkrst->crc_cpu_cmplx_clr);
491 unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
496 unsigned clock_get_rate(enum clock_id clkid)
500 u64 parent_rate, rate;
501 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
503 parent_rate = osc_freq[clock_get_osc_freq()];
504 if (clkid == CLOCK_ID_OSC)
507 if (clkid == CLOCK_ID_CLK_M)
508 return clk_m_get_rate(parent_rate);
510 pll = get_pll(clkid);
513 base = readl(&pll->pll_base);
515 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
516 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
518 * PLLU uses p_mask/p_shift for VCO on all but T210,
519 * T210 uses normal DIVP. Handled in pllinfo table.
521 #ifdef CONFIG_TEGRA210
523 * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
524 * not applied. pllP_out2 does have divp applied. All other pllP_outN
525 * are divided down from pllP_out0. We only support pllP_out0 in
526 * U-Boot at the time of writing this comment.
528 if (clkid != CLOCK_ID_PERIPH)
530 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
536 * Set the output frequency you want for each PLL clock.
537 * PLL output frequencies are programmed by setting their N, M and P values.
538 * The governing equations are:
539 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
540 * where Fo is the output frequency from the PLL.
541 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
542 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
543 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
545 * @param n PLL feedback divider(DIVN)
546 * @param m PLL input divider(DIVN)
547 * @param p post divider(DIVP)
548 * @param cpcon base PLL charge pump(CPCON)
549 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
550 * be overridden), 1 if PLL is already correct
552 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
554 u32 base_reg, misc_reg;
556 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
558 pll = get_pll(clkid);
560 base_reg = readl(&pll->pll_base);
562 /* Set BYPASS, m, n and p to PLL_BASE */
563 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
564 base_reg |= m << pllinfo->m_shift;
566 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
567 base_reg |= n << pllinfo->n_shift;
569 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
570 base_reg |= p << pllinfo->p_shift;
572 if (clkid == CLOCK_ID_PERIPH) {
574 * If the PLL is already set up, check that it is correct
575 * and record this info for clock_verify() to check.
577 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
578 base_reg |= PLL_ENABLE_MASK;
579 if (base_reg != readl(&pll->pll_base))
581 return pllp_valid ? 1 : -1;
583 base_reg |= PLL_BASE_OVRRIDE_MASK;
586 base_reg |= PLL_BYPASS_MASK;
587 writel(base_reg, &pll->pll_base);
589 /* Set cpcon (KCP) to PLL_MISC */
590 misc_reg = readl(&pll->pll_misc);
591 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
592 misc_reg |= cpcon << pllinfo->kcp_shift;
593 writel(misc_reg, &pll->pll_misc);
596 base_reg |= PLL_ENABLE_MASK;
597 writel(base_reg, &pll->pll_base);
600 base_reg &= ~PLL_BYPASS_MASK;
601 writel(base_reg, &pll->pll_base);
606 void clock_ll_start_uart(enum periph_id periph_id)
608 /* Assert UART reset and enable clock */
609 reset_set_enable(periph_id, 1);
610 clock_enable(periph_id);
611 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
616 /* De-assert reset to UART */
617 reset_set_enable(periph_id, 0);
620 #if CONFIG_IS_ENABLED(OF_CONTROL)
621 int clock_decode_periph_id(const void *blob, int node)
627 err = fdtdec_get_int_array(blob, node, "clocks", cell,
631 id = clk_id_to_periph_id(cell[1]);
632 assert(clock_periph_id_isvalid(id));
635 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
637 int clock_verify(void)
639 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
640 u32 reg = readl(&pll->pll_base);
643 printf("Warning: PLLP %x is not correct\n", reg);
646 debug("PLLP %x is correct\n", reg);
650 void clock_init(void)
654 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
655 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
656 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
657 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
658 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
659 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
660 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
661 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
662 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
664 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
665 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
666 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
667 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
668 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
669 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
670 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
671 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
673 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
674 enum periph_id periph_id;
675 enum clock_id parent;
676 int source, mux_bits, divider_bits;
678 periph_id = periph_clk_init_table[i].periph_id;
679 parent = periph_clk_init_table[i].parent_clock_id;
681 source = get_periph_clock_source(periph_id, parent, &mux_bits,
683 clock_ll_set_source_bits(periph_id, mux_bits, source);
687 static void set_avp_clock_source(u32 src)
689 struct clk_rst_ctlr *clkrst =
690 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
693 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
694 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
695 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
696 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
697 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
698 writel(val, &clkrst->crc_sclk_brst_pol);
703 * This function is useful on Tegra30, and any later SoCs that have compatible
704 * PLLP configuration registers.
705 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
707 void tegra30_set_up_pllp(void)
709 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
713 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
714 * run up to 275MHz. On power on, the default sytem clock source is set
715 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
716 * 408MHz which is beyond system clock's upper limit.
718 * The fix is to set the system clock to CLK_M before initializing PLLP,
719 * and then switch back to PLLP_OUT4, which has an appropriate divider
720 * configured, after PLLP has been configured
722 set_avp_clock_source(SCLK_SOURCE_CLKM);
725 * PLLP output frequency set to 408Mhz
726 * PLLC output frequency set to 228Mhz
728 switch (clock_get_osc_freq()) {
729 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
730 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
731 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
734 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
735 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
736 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
739 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
740 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
741 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
743 case CLOCK_OSC_FREQ_19_2:
746 * These are not supported. It is too early to print a
747 * message and the UART likely won't work anyway due to the
748 * oscillator being wrong.
753 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
756 /* Assert RSTN before enable */
757 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
758 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
759 /* Set divisor and reenable */
760 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
761 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
762 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
763 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
764 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
767 /* Assert RSTN before enable */
768 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
769 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
770 /* Set divisor and reenable */
771 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
772 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
773 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
774 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
775 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
777 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
780 int clock_external_output(int clk_id)
782 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
784 if (clk_id >= 1 && clk_id <= 3) {
785 setbits_le32(&pmc->pmc_clk_out_cntrl,
786 1 << (2 + (clk_id - 1) * 8));
788 printf("%s: Unknown output clock id %d\n", __func__, clk_id);