2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra SoC common clock control functions */
22 #include <asm/arch/clock.h>
23 #include <asm/arch/tegra.h>
24 #include <asm/arch-tegra/ap.h>
25 #include <asm/arch-tegra/clk_rst.h>
26 #include <asm/arch-tegra/pmc.h>
27 #include <asm/arch-tegra/timer.h>
32 * This is our record of the current clock rate of each clock. We don't
33 * fill all of these in since we are only really interested in clocks which
36 static unsigned pll_rate[CLOCK_ID_COUNT];
39 * The oscillator frequency is fixed to one of four set values. Based on this
40 * the other clocks are set up appropriately.
42 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
51 /* return 1 if a peripheral ID is in range */
52 #define clock_type_id_isvalid(id) ((id) >= 0 && \
53 (id) < CLOCK_TYPE_COUNT)
55 char pllp_valid = 1; /* PLLP is set up correctly */
57 /* return 1 if a periphc_internal_id is in range */
58 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
61 /* number of clock outputs of a PLL */
62 static const u8 pll_num_clkouts[] = {
71 int clock_get_osc_bypass(void)
73 struct clk_rst_ctlr *clkrst =
74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
77 reg = readl(&clkrst->crc_osc_ctrl);
78 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
81 /* Returns a pointer to the registers of the given pll */
82 static struct clk_pll *get_pll(enum clock_id clkid)
84 struct clk_rst_ctlr *clkrst =
85 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
87 assert(clock_id_is_pll(clkid));
88 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
89 debug("%s: Invalid PLL %d\n", __func__, clkid);
92 return &clkrst->crc_pll[clkid];
95 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
100 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
101 u32 *divp, u32 *cpcon, u32 *lfcon)
103 struct clk_pll *pll = get_pll(clkid);
104 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
107 assert(clkid != CLOCK_ID_USB);
109 /* Safety check, adds to code size but is small */
110 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
112 data = readl(&pll->pll_base);
113 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
114 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
115 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
116 data = readl(&pll->pll_misc);
117 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
118 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
119 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
124 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
125 u32 divp, u32 cpcon, u32 lfcon)
127 struct clk_pll *pll = NULL;
128 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
129 struct clk_pll_simple *simple_pll = NULL;
132 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
133 pll = get_pll(clkid);
135 simple_pll = clock_get_simple_pll(clkid);
137 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
143 * pllinfo has the m/n/p and kcp/kvco mask and shift
144 * values for all of the PLLs used in U-Boot, with any
145 * SoC differences accounted for.
147 * Preserve EN_LOCKDET, etc.
150 misc_data = readl(&pll->pll_misc);
152 misc_data = readl(&simple_pll->pll_misc);
153 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
154 misc_data |= cpcon << pllinfo->kcp_shift;
155 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
156 misc_data |= lfcon << pllinfo->kvco_shift;
158 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
159 data |= divp << pllinfo->p_shift;
160 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
163 writel(misc_data, &pll->pll_misc);
164 writel(data, &pll->pll_base);
166 writel(misc_data, &simple_pll->pll_misc);
167 writel(data, &simple_pll->pll_base);
170 /* calculate the stable time */
171 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
174 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
177 u32 *reg = get_periph_source_reg(periph_id);
182 value &= ~OUT_CLK_SOURCE_31_30_MASK;
183 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
185 value &= ~OUT_CLK_DIVISOR_MASK;
186 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
191 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
194 u32 *reg = get_periph_source_reg(periph_id);
197 case MASK_BITS_31_30:
198 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
199 source << OUT_CLK_SOURCE_31_30_SHIFT);
202 case MASK_BITS_31_29:
203 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
204 source << OUT_CLK_SOURCE_31_29_SHIFT);
207 case MASK_BITS_31_28:
208 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
209 source << OUT_CLK_SOURCE_31_28_SHIFT);
219 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
221 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
225 * Given the parent's rate and the required rate for the children, this works
226 * out the peripheral clock divider to use, in 7.1 binary format.
228 * @param divider_bits number of divider bits (8 or 16)
229 * @param parent_rate clock rate of parent clock in Hz
230 * @param rate required clock rate for this clock
231 * @return divider which should be used
233 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
236 u64 divider = parent_rate * 2;
237 unsigned max_divider = 1 << divider_bits;
240 do_div(divider, rate);
242 if ((s64)divider - 2 < 0)
245 if ((s64)divider - 2 >= max_divider)
251 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
253 struct clk_pll *pll = get_pll(clkid);
254 int data = 0, div = 0, offset = 0;
256 if (!clock_id_is_pll(clkid))
259 if (pllout + 1 > pll_num_clkouts[clkid])
262 div = clk_get_divider(8, pll_rate[clkid], rate);
267 /* out2 and out4 are in the high part of the register */
268 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
271 data = (div << PLL_OUT_RATIO_SHIFT) |
272 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
273 clrsetbits_le32(&pll->pll_out[pllout >> 1],
274 PLL_OUT_RATIO_MASK << offset, data << offset);
280 * Given the parent's rate and the divider in 7.1 format, this works out the
281 * resulting peripheral clock rate.
283 * @param parent_rate clock rate of parent clock in Hz
284 * @param divider which should be used in 7.1 format
285 * @return effective clock rate of peripheral
287 static unsigned long get_rate_from_divider(unsigned long parent_rate,
292 rate = (u64)parent_rate * 2;
293 do_div(rate, divider + 2);
297 unsigned long clock_get_periph_rate(enum periph_id periph_id,
298 enum clock_id parent)
300 u32 *reg = get_periph_source_reg(periph_id);
302 return get_rate_from_divider(pll_rate[parent],
303 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
307 * Find the best available 7.1 format divisor given a parent clock rate and
308 * required child clock rate. This function assumes that a second-stage
309 * divisor is available which can divide by powers of 2 from 1 to 256.
311 * @param divider_bits number of divider bits (8 or 16)
312 * @param parent_rate clock rate of parent clock in Hz
313 * @param rate required clock rate for this clock
314 * @param extra_div value for the second-stage divisor (not set if this
315 * function returns -1.
316 * @return divider which should be used, or -1 if nothing is valid
319 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
320 unsigned long rate, int *extra_div)
323 int best_divider = -1;
324 int best_error = rate;
326 /* try dividers from 1 to 256 and find closest match */
327 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
328 unsigned divided_parent = parent_rate >> shift;
329 int divider = clk_get_divider(divider_bits, divided_parent,
331 unsigned effective_rate = get_rate_from_divider(divided_parent,
333 int error = rate - effective_rate;
335 /* Given a valid divider, look for the lowest error */
336 if (divider != -1 && error < best_error) {
338 *extra_div = 1 << shift;
339 best_divider = divider;
343 /* return what we found - *extra_div will already be set */
348 * Adjust peripheral PLL to use the given divider and source.
350 * @param periph_id peripheral to adjust
351 * @param source Source number (0-3 or 0-7)
352 * @param mux_bits Number of mux bits (2 or 4)
353 * @param divider Required divider in 7.1 or 15.1 format
354 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
355 * for this peripheral)
357 static int adjust_periph_pll(enum periph_id periph_id, int source,
358 int mux_bits, unsigned divider)
360 u32 *reg = get_periph_source_reg(periph_id);
362 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
363 divider << OUT_CLK_DIVISOR_SHIFT);
366 /* work out the source clock and set it */
370 clock_ll_set_source_bits(periph_id, mux_bits, source);
376 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
377 enum clock_id parent, unsigned rate, int *extra_div)
379 unsigned effective_rate;
380 int mux_bits, divider_bits, source;
384 /* work out the source clock and set it */
385 source = get_periph_clock_source(periph_id, parent, &mux_bits,
388 divider = find_best_divider(divider_bits, pll_rate[parent],
393 assert(divider >= 0);
394 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
396 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
397 get_periph_source_reg(periph_id),
398 readl(get_periph_source_reg(periph_id)));
400 /* Check what we ended up with. This shouldn't matter though */
401 effective_rate = clock_get_periph_rate(periph_id, parent);
403 effective_rate /= *extra_div;
404 if (rate != effective_rate)
405 debug("Requested clock rate %u not honored (got %u)\n",
406 rate, effective_rate);
407 return effective_rate;
410 unsigned clock_start_periph_pll(enum periph_id periph_id,
411 enum clock_id parent, unsigned rate)
413 unsigned effective_rate;
415 reset_set_enable(periph_id, 1);
416 clock_enable(periph_id);
418 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
421 reset_set_enable(periph_id, 0);
422 return effective_rate;
425 void clock_enable(enum periph_id clkid)
427 clock_set_enable(clkid, 1);
430 void clock_disable(enum periph_id clkid)
432 clock_set_enable(clkid, 0);
435 void reset_periph(enum periph_id periph_id, int us_delay)
437 /* Put peripheral into reset */
438 reset_set_enable(periph_id, 1);
442 reset_set_enable(periph_id, 0);
447 void reset_cmplx_set_enable(int cpu, int which, int reset)
449 struct clk_rst_ctlr *clkrst =
450 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
453 /* Form the mask, which depends on the cpu chosen (2 or 4) */
454 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
457 /* either enable or disable those reset for that CPU */
459 writel(mask, &clkrst->crc_cpu_cmplx_set);
461 writel(mask, &clkrst->crc_cpu_cmplx_clr);
464 unsigned clock_get_rate(enum clock_id clkid)
468 u64 parent_rate, rate;
469 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
471 parent_rate = osc_freq[clock_get_osc_freq()];
472 if (clkid == CLOCK_ID_OSC)
475 pll = get_pll(clkid);
478 base = readl(&pll->pll_base);
480 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
481 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
483 * PLLU uses p_mask/p_shift for VCO on all but T210,
484 * T210 uses normal DIVP. Handled in pllinfo table.
486 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
492 * Set the output frequency you want for each PLL clock.
493 * PLL output frequencies are programmed by setting their N, M and P values.
494 * The governing equations are:
495 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
496 * where Fo is the output frequency from the PLL.
497 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
498 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
499 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
501 * @param n PLL feedback divider(DIVN)
502 * @param m PLL input divider(DIVN)
503 * @param p post divider(DIVP)
504 * @param cpcon base PLL charge pump(CPCON)
505 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
506 * be overriden), 1 if PLL is already correct
508 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
510 u32 base_reg, misc_reg;
512 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
514 pll = get_pll(clkid);
516 base_reg = readl(&pll->pll_base);
518 /* Set BYPASS, m, n and p to PLL_BASE */
519 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
520 base_reg |= m << pllinfo->m_shift;
522 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
523 base_reg |= n << pllinfo->n_shift;
525 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
526 base_reg |= p << pllinfo->p_shift;
528 if (clkid == CLOCK_ID_PERIPH) {
530 * If the PLL is already set up, check that it is correct
531 * and record this info for clock_verify() to check.
533 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
534 base_reg |= PLL_ENABLE_MASK;
535 if (base_reg != readl(&pll->pll_base))
537 return pllp_valid ? 1 : -1;
539 base_reg |= PLL_BASE_OVRRIDE_MASK;
542 base_reg |= PLL_BYPASS_MASK;
543 writel(base_reg, &pll->pll_base);
545 /* Set cpcon (KCP) to PLL_MISC */
546 misc_reg = readl(&pll->pll_misc);
547 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
548 misc_reg |= cpcon << pllinfo->kcp_shift;
549 writel(misc_reg, &pll->pll_misc);
552 base_reg |= PLL_ENABLE_MASK;
553 writel(base_reg, &pll->pll_base);
556 base_reg &= ~PLL_BYPASS_MASK;
557 writel(base_reg, &pll->pll_base);
562 void clock_ll_start_uart(enum periph_id periph_id)
564 /* Assert UART reset and enable clock */
565 reset_set_enable(periph_id, 1);
566 clock_enable(periph_id);
567 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
572 /* De-assert reset to UART */
573 reset_set_enable(periph_id, 0);
576 #if CONFIG_IS_ENABLED(OF_CONTROL)
577 int clock_decode_periph_id(const void *blob, int node)
583 err = fdtdec_get_int_array(blob, node, "clocks", cell,
587 id = clk_id_to_periph_id(cell[1]);
588 assert(clock_periph_id_isvalid(id));
591 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
593 int clock_verify(void)
595 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
596 u32 reg = readl(&pll->pll_base);
599 printf("Warning: PLLP %x is not correct\n", reg);
602 debug("PLLP %x is correct\n", reg);
606 void clock_init(void)
608 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
609 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
610 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
611 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
612 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
613 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
614 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
615 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
617 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
618 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
619 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
620 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
621 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
622 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
623 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
626 static void set_avp_clock_source(u32 src)
628 struct clk_rst_ctlr *clkrst =
629 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
632 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
633 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
634 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
635 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
636 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
637 writel(val, &clkrst->crc_sclk_brst_pol);
642 * This function is useful on Tegra30, and any later SoCs that have compatible
643 * PLLP configuration registers.
644 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
646 void tegra30_set_up_pllp(void)
648 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
652 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
653 * run up to 275MHz. On power on, the default sytem clock source is set
654 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
655 * 408MHz which is beyond system clock's upper limit.
657 * The fix is to set the system clock to CLK_M before initializing PLLP,
658 * and then switch back to PLLP_OUT4, which has an appropriate divider
659 * configured, after PLLP has been configured
661 set_avp_clock_source(SCLK_SOURCE_CLKM);
664 * PLLP output frequency set to 408Mhz
665 * PLLC output frequency set to 228Mhz
667 switch (clock_get_osc_freq()) {
668 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
669 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
670 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
673 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
674 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
675 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
678 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
679 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
680 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
682 case CLOCK_OSC_FREQ_19_2:
685 * These are not supported. It is too early to print a
686 * message and the UART likely won't work anyway due to the
687 * oscillator being wrong.
692 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
695 /* Assert RSTN before enable */
696 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
697 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
698 /* Set divisor and reenable */
699 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
700 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
701 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
702 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
703 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
706 /* Assert RSTN before enable */
707 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
708 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
709 /* Set divisor and reenable */
710 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
711 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
712 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
713 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
714 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
716 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
719 int clock_external_output(int clk_id)
721 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
723 if (clk_id >= 1 && clk_id <= 3) {
724 setbits_le32(&pmc->pmc_clk_out_cntrl,
725 1 << (2 + (clk_id - 1) * 8));
727 printf("%s: Unknown output clock id %d\n", __func__, clk_id);