2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra SoC common clock control functions */
21 #include <asm/arch/clock.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/ap.h>
24 #include <asm/arch-tegra/clk_rst.h>
25 #include <asm/arch-tegra/timer.h>
30 * This is our record of the current clock rate of each clock. We don't
31 * fill all of these in since we are only really interested in clocks which
34 static unsigned pll_rate[CLOCK_ID_COUNT];
37 * The oscillator frequency is fixed to one of four set values. Based on this
38 * the other clocks are set up appropriately.
40 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
47 /* return 1 if a peripheral ID is in range */
48 #define clock_type_id_isvalid(id) ((id) >= 0 && \
49 (id) < CLOCK_TYPE_COUNT)
51 char pllp_valid = 1; /* PLLP is set up correctly */
53 /* return 1 if a periphc_internal_id is in range */
54 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
57 /* number of clock outputs of a PLL */
58 static const u8 pll_num_clkouts[] = {
67 int clock_get_osc_bypass(void)
69 struct clk_rst_ctlr *clkrst =
70 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
73 reg = readl(&clkrst->crc_osc_ctrl);
74 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
77 /* Returns a pointer to the registers of the given pll */
78 static struct clk_pll *get_pll(enum clock_id clkid)
80 struct clk_rst_ctlr *clkrst =
81 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
83 assert(clock_id_is_pll(clkid));
84 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
85 debug("%s: Invalid PLL\n", __func__);
88 return &clkrst->crc_pll[clkid];
91 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
96 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
97 u32 *divp, u32 *cpcon, u32 *lfcon)
99 struct clk_pll *pll = get_pll(clkid);
102 assert(clkid != CLOCK_ID_USB);
104 /* Safety check, adds to code size but is small */
105 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
107 data = readl(&pll->pll_base);
108 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
109 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
110 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
111 data = readl(&pll->pll_misc);
112 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
113 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
118 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
119 u32 divp, u32 cpcon, u32 lfcon)
121 struct clk_pll *pll = get_pll(clkid);
125 * We cheat by treating all PLL (except PLLU) in the same fashion.
126 * This works only because:
127 * - same fields are always mapped at same offsets, except DCCON
128 * - DCCON is always 0, doesn't conflict
129 * - M,N, P of PLLP values are ignored for PLLP
131 misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
133 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
134 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
136 if (clkid == CLOCK_ID_USB)
137 data |= divp << PLLU_VCO_FREQ_SHIFT;
139 data |= divp << PLL_DIVP_SHIFT;
141 writel(misc_data, &pll->pll_misc);
142 writel(data, &pll->pll_base);
144 struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
147 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
150 writel(misc_data, &pll->pll_misc);
151 writel(data, &pll->pll_base);
154 /* calculate the stable time */
155 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
158 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
161 u32 *reg = get_periph_source_reg(periph_id);
166 value &= ~OUT_CLK_SOURCE_31_30_MASK;
167 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
169 value &= ~OUT_CLK_DIVISOR_MASK;
170 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
175 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
178 u32 *reg = get_periph_source_reg(periph_id);
181 case MASK_BITS_31_30:
182 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
183 source << OUT_CLK_SOURCE_31_30_SHIFT);
186 case MASK_BITS_31_29:
187 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
188 source << OUT_CLK_SOURCE_31_29_SHIFT);
191 case MASK_BITS_31_28:
192 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
193 source << OUT_CLK_SOURCE_31_28_SHIFT);
203 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
205 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
209 * Given the parent's rate and the required rate for the children, this works
210 * out the peripheral clock divider to use, in 7.1 binary format.
212 * @param divider_bits number of divider bits (8 or 16)
213 * @param parent_rate clock rate of parent clock in Hz
214 * @param rate required clock rate for this clock
215 * @return divider which should be used
217 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
220 u64 divider = parent_rate * 2;
221 unsigned max_divider = 1 << divider_bits;
224 do_div(divider, rate);
226 if ((s64)divider - 2 < 0)
229 if ((s64)divider - 2 >= max_divider)
235 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
237 struct clk_pll *pll = get_pll(clkid);
238 int data = 0, div = 0, offset = 0;
240 if (!clock_id_is_pll(clkid))
243 if (pllout + 1 > pll_num_clkouts[clkid])
246 div = clk_get_divider(8, pll_rate[clkid], rate);
251 /* out2 and out4 are in the high part of the register */
252 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
255 data = (div << PLL_OUT_RATIO_SHIFT) |
256 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
257 clrsetbits_le32(&pll->pll_out[pllout >> 1],
258 PLL_OUT_RATIO_MASK << offset, data << offset);
264 * Given the parent's rate and the divider in 7.1 format, this works out the
265 * resulting peripheral clock rate.
267 * @param parent_rate clock rate of parent clock in Hz
268 * @param divider which should be used in 7.1 format
269 * @return effective clock rate of peripheral
271 static unsigned long get_rate_from_divider(unsigned long parent_rate,
276 rate = (u64)parent_rate * 2;
277 do_div(rate, divider + 2);
281 unsigned long clock_get_periph_rate(enum periph_id periph_id,
282 enum clock_id parent)
284 u32 *reg = get_periph_source_reg(periph_id);
286 return get_rate_from_divider(pll_rate[parent],
287 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
291 * Find the best available 7.1 format divisor given a parent clock rate and
292 * required child clock rate. This function assumes that a second-stage
293 * divisor is available which can divide by powers of 2 from 1 to 256.
295 * @param divider_bits number of divider bits (8 or 16)
296 * @param parent_rate clock rate of parent clock in Hz
297 * @param rate required clock rate for this clock
298 * @param extra_div value for the second-stage divisor (not set if this
299 * function returns -1.
300 * @return divider which should be used, or -1 if nothing is valid
303 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
304 unsigned long rate, int *extra_div)
307 int best_divider = -1;
308 int best_error = rate;
310 /* try dividers from 1 to 256 and find closest match */
311 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
312 unsigned divided_parent = parent_rate >> shift;
313 int divider = clk_get_divider(divider_bits, divided_parent,
315 unsigned effective_rate = get_rate_from_divider(divided_parent,
317 int error = rate - effective_rate;
319 /* Given a valid divider, look for the lowest error */
320 if (divider != -1 && error < best_error) {
322 *extra_div = 1 << shift;
323 best_divider = divider;
327 /* return what we found - *extra_div will already be set */
332 * Adjust peripheral PLL to use the given divider and source.
334 * @param periph_id peripheral to adjust
335 * @param source Source number (0-3 or 0-7)
336 * @param mux_bits Number of mux bits (2 or 4)
337 * @param divider Required divider in 7.1 or 15.1 format
338 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
339 * for this peripheral)
341 static int adjust_periph_pll(enum periph_id periph_id, int source,
342 int mux_bits, unsigned divider)
344 u32 *reg = get_periph_source_reg(periph_id);
346 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
347 divider << OUT_CLK_DIVISOR_SHIFT);
350 /* work out the source clock and set it */
354 clock_ll_set_source_bits(periph_id, mux_bits, source);
360 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
361 enum clock_id parent, unsigned rate, int *extra_div)
363 unsigned effective_rate;
364 int mux_bits, divider_bits, source;
368 /* work out the source clock and set it */
369 source = get_periph_clock_source(periph_id, parent, &mux_bits,
372 divider = find_best_divider(divider_bits, pll_rate[parent],
377 assert(divider >= 0);
378 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
380 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
381 get_periph_source_reg(periph_id),
382 readl(get_periph_source_reg(periph_id)));
384 /* Check what we ended up with. This shouldn't matter though */
385 effective_rate = clock_get_periph_rate(periph_id, parent);
387 effective_rate /= *extra_div;
388 if (rate != effective_rate)
389 debug("Requested clock rate %u not honored (got %u)\n",
390 rate, effective_rate);
391 return effective_rate;
394 unsigned clock_start_periph_pll(enum periph_id periph_id,
395 enum clock_id parent, unsigned rate)
397 unsigned effective_rate;
399 reset_set_enable(periph_id, 1);
400 clock_enable(periph_id);
402 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
405 reset_set_enable(periph_id, 0);
406 return effective_rate;
409 void clock_enable(enum periph_id clkid)
411 clock_set_enable(clkid, 1);
414 void clock_disable(enum periph_id clkid)
416 clock_set_enable(clkid, 0);
419 void reset_periph(enum periph_id periph_id, int us_delay)
421 /* Put peripheral into reset */
422 reset_set_enable(periph_id, 1);
426 reset_set_enable(periph_id, 0);
431 void reset_cmplx_set_enable(int cpu, int which, int reset)
433 struct clk_rst_ctlr *clkrst =
434 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
437 /* Form the mask, which depends on the cpu chosen (2 or 4) */
438 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
441 /* either enable or disable those reset for that CPU */
443 writel(mask, &clkrst->crc_cpu_cmplx_set);
445 writel(mask, &clkrst->crc_cpu_cmplx_clr);
448 unsigned clock_get_rate(enum clock_id clkid)
456 parent_rate = osc_freq[clock_get_osc_freq()];
457 if (clkid == CLOCK_ID_OSC)
460 pll = get_pll(clkid);
463 base = readl(&pll->pll_base);
465 /* Oh for bf_unpack()... */
466 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
467 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
468 if (clkid == CLOCK_ID_USB)
469 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
471 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
477 * Set the output frequency you want for each PLL clock.
478 * PLL output frequencies are programmed by setting their N, M and P values.
479 * The governing equations are:
480 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
481 * where Fo is the output frequency from the PLL.
482 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
483 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
484 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
486 * @param n PLL feedback divider(DIVN)
487 * @param m PLL input divider(DIVN)
488 * @param p post divider(DIVP)
489 * @param cpcon base PLL charge pump(CPCON)
490 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
491 * be overriden), 1 if PLL is already correct
493 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
499 pll = get_pll(clkid);
501 base_reg = readl(&pll->pll_base);
503 /* Set BYPASS, m, n and p to PLL_BASE */
504 base_reg &= ~PLL_DIVM_MASK;
505 base_reg |= m << PLL_DIVM_SHIFT;
507 base_reg &= ~PLL_DIVN_MASK;
508 base_reg |= n << PLL_DIVN_SHIFT;
510 base_reg &= ~PLL_DIVP_MASK;
511 base_reg |= p << PLL_DIVP_SHIFT;
513 if (clkid == CLOCK_ID_PERIPH) {
515 * If the PLL is already set up, check that it is correct
516 * and record this info for clock_verify() to check.
518 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
519 base_reg |= PLL_ENABLE_MASK;
520 if (base_reg != readl(&pll->pll_base))
522 return pllp_valid ? 1 : -1;
524 base_reg |= PLL_BASE_OVRRIDE_MASK;
527 base_reg |= PLL_BYPASS_MASK;
528 writel(base_reg, &pll->pll_base);
530 /* Set cpcon to PLL_MISC */
531 misc_reg = readl(&pll->pll_misc);
532 misc_reg &= ~PLL_CPCON_MASK;
533 misc_reg |= cpcon << PLL_CPCON_SHIFT;
534 writel(misc_reg, &pll->pll_misc);
537 base_reg |= PLL_ENABLE_MASK;
538 writel(base_reg, &pll->pll_base);
541 base_reg &= ~PLL_BYPASS_MASK;
542 writel(base_reg, &pll->pll_base);
547 void clock_ll_start_uart(enum periph_id periph_id)
549 /* Assert UART reset and enable clock */
550 reset_set_enable(periph_id, 1);
551 clock_enable(periph_id);
552 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
557 /* De-assert reset to UART */
558 reset_set_enable(periph_id, 0);
561 #ifdef CONFIG_OF_CONTROL
562 int clock_decode_periph_id(const void *blob, int node)
568 err = fdtdec_get_int_array(blob, node, "clocks", cell,
572 id = clk_id_to_periph_id(cell[1]);
573 assert(clock_periph_id_isvalid(id));
576 #endif /* CONFIG_OF_CONTROL */
578 int clock_verify(void)
580 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
581 u32 reg = readl(&pll->pll_base);
584 printf("Warning: PLLP %x is not correct\n", reg);
587 debug("PLLP %x is correct\n", reg);
591 void clock_init(void)
593 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
594 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
595 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
596 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
597 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
598 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
599 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
600 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
601 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
602 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
603 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
604 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
605 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
607 /* Do any special system timer/TSC setup */
608 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
609 if (!tegra_cpu_is_non_secure())
614 static void set_avp_clock_source(u32 src)
616 struct clk_rst_ctlr *clkrst =
617 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
620 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
621 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
622 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
623 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
624 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
625 writel(val, &clkrst->crc_sclk_brst_pol);
630 * This function is useful on Tegra30, and any later SoCs that have compatible
631 * PLLP configuration registers.
633 void tegra30_set_up_pllp(void)
635 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
639 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
640 * run up to 275MHz. On power on, the default sytem clock source is set
641 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
642 * 408MHz which is beyond system clock's upper limit.
644 * The fix is to set the system clock to CLK_M before initializing PLLP,
645 * and then switch back to PLLP_OUT4, which has an appropriate divider
646 * configured, after PLLP has been configured
648 set_avp_clock_source(SCLK_SOURCE_CLKM);
651 * PLLP output frequency set to 408Mhz
652 * PLLC output frequency set to 228Mhz
654 switch (clock_get_osc_freq()) {
655 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
656 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
657 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
660 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
661 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
662 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
665 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
666 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
667 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
669 case CLOCK_OSC_FREQ_19_2:
672 * These are not supported. It is too early to print a
673 * message and the UART likely won't work anyway due to the
674 * oscillator being wrong.
679 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
682 /* Assert RSTN before enable */
683 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
684 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
685 /* Set divisor and reenable */
686 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
687 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
688 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
689 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
690 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
693 /* Assert RSTN before enable */
694 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
695 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
696 /* Set divisor and reenable */
697 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
698 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
699 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
700 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
701 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
703 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);