2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra SoC common clock control functions */
22 #include <asm/arch/clock.h>
23 #include <asm/arch/tegra.h>
24 #include <asm/arch-tegra/ap.h>
25 #include <asm/arch-tegra/clk_rst.h>
26 #include <asm/arch-tegra/pmc.h>
27 #include <asm/arch-tegra/timer.h>
32 * This is our record of the current clock rate of each clock. We don't
33 * fill all of these in since we are only really interested in clocks which
36 static unsigned pll_rate[CLOCK_ID_COUNT];
39 * The oscillator frequency is fixed to one of four set values. Based on this
40 * the other clocks are set up appropriately.
42 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
49 /* return 1 if a peripheral ID is in range */
50 #define clock_type_id_isvalid(id) ((id) >= 0 && \
51 (id) < CLOCK_TYPE_COUNT)
53 char pllp_valid = 1; /* PLLP is set up correctly */
55 /* return 1 if a periphc_internal_id is in range */
56 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
59 /* number of clock outputs of a PLL */
60 static const u8 pll_num_clkouts[] = {
69 int clock_get_osc_bypass(void)
71 struct clk_rst_ctlr *clkrst =
72 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
75 reg = readl(&clkrst->crc_osc_ctrl);
76 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
79 /* Returns a pointer to the registers of the given pll */
80 static struct clk_pll *get_pll(enum clock_id clkid)
82 struct clk_rst_ctlr *clkrst =
83 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
85 assert(clock_id_is_pll(clkid));
86 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
87 debug("%s: Invalid PLL %d\n", __func__, clkid);
90 return &clkrst->crc_pll[clkid];
93 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
98 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
99 u32 *divp, u32 *cpcon, u32 *lfcon)
101 struct clk_pll *pll = get_pll(clkid);
104 assert(clkid != CLOCK_ID_USB);
106 /* Safety check, adds to code size but is small */
107 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
109 data = readl(&pll->pll_base);
110 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
111 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
112 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
113 data = readl(&pll->pll_misc);
114 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
115 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
116 #if defined(CONFIG_TEGRA210)
117 /* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */
118 *cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT;
119 *lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT;
124 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
125 u32 divp, u32 cpcon, u32 lfcon)
127 struct clk_pll *pll = NULL;
130 if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
131 pll = get_pll(clkid);
134 * We cheat by treating all PLL (except PLLU) in the same fashion.
135 * This works only because:
136 * - same fields are always mapped at same offsets, except DCCON
137 * - DCCON is always 0, doesn't conflict
138 * - M,N, P of PLLP values are ignored for PLLP
139 * NOTE: Above is no longer true with T210 - TBD: FIX THIS
141 misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
143 #if defined(CONFIG_TEGRA210)
144 /* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */
145 if (clkid == CLOCK_ID_USB) {
146 /* preserve EN_LOCKDET, set by default */
147 misc_data = readl(&pll->pll_misc);
148 misc_data |= (cpcon << PLLU_KCP_SHIFT) |
149 (lfcon << PLLU_KVCO_SHIFT);
152 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
153 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
155 if (clkid == CLOCK_ID_USB)
156 #if defined(CONFIG_TEGRA210)
157 data |= divp << PLLU_DIVP_SHIFT;
159 data |= divp << PLLU_VCO_FREQ_SHIFT;
162 data |= divp << PLL_DIVP_SHIFT;
164 writel(misc_data, &pll->pll_misc);
165 writel(data, &pll->pll_base);
167 struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
170 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
173 writel(misc_data, &pll->pll_misc);
174 writel(data, &pll->pll_base);
177 /* calculate the stable time */
178 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
181 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
184 u32 *reg = get_periph_source_reg(periph_id);
189 value &= ~OUT_CLK_SOURCE_31_30_MASK;
190 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
192 value &= ~OUT_CLK_DIVISOR_MASK;
193 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
198 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
201 u32 *reg = get_periph_source_reg(periph_id);
204 case MASK_BITS_31_30:
205 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
206 source << OUT_CLK_SOURCE_31_30_SHIFT);
209 case MASK_BITS_31_29:
210 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
211 source << OUT_CLK_SOURCE_31_29_SHIFT);
214 case MASK_BITS_31_28:
215 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
216 source << OUT_CLK_SOURCE_31_28_SHIFT);
226 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
228 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
232 * Given the parent's rate and the required rate for the children, this works
233 * out the peripheral clock divider to use, in 7.1 binary format.
235 * @param divider_bits number of divider bits (8 or 16)
236 * @param parent_rate clock rate of parent clock in Hz
237 * @param rate required clock rate for this clock
238 * @return divider which should be used
240 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
243 u64 divider = parent_rate * 2;
244 unsigned max_divider = 1 << divider_bits;
247 do_div(divider, rate);
249 if ((s64)divider - 2 < 0)
252 if ((s64)divider - 2 >= max_divider)
258 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
260 struct clk_pll *pll = get_pll(clkid);
261 int data = 0, div = 0, offset = 0;
263 if (!clock_id_is_pll(clkid))
266 if (pllout + 1 > pll_num_clkouts[clkid])
269 div = clk_get_divider(8, pll_rate[clkid], rate);
274 /* out2 and out4 are in the high part of the register */
275 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
278 data = (div << PLL_OUT_RATIO_SHIFT) |
279 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
280 clrsetbits_le32(&pll->pll_out[pllout >> 1],
281 PLL_OUT_RATIO_MASK << offset, data << offset);
287 * Given the parent's rate and the divider in 7.1 format, this works out the
288 * resulting peripheral clock rate.
290 * @param parent_rate clock rate of parent clock in Hz
291 * @param divider which should be used in 7.1 format
292 * @return effective clock rate of peripheral
294 static unsigned long get_rate_from_divider(unsigned long parent_rate,
299 rate = (u64)parent_rate * 2;
300 do_div(rate, divider + 2);
304 unsigned long clock_get_periph_rate(enum periph_id periph_id,
305 enum clock_id parent)
307 u32 *reg = get_periph_source_reg(periph_id);
309 return get_rate_from_divider(pll_rate[parent],
310 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
314 * Find the best available 7.1 format divisor given a parent clock rate and
315 * required child clock rate. This function assumes that a second-stage
316 * divisor is available which can divide by powers of 2 from 1 to 256.
318 * @param divider_bits number of divider bits (8 or 16)
319 * @param parent_rate clock rate of parent clock in Hz
320 * @param rate required clock rate for this clock
321 * @param extra_div value for the second-stage divisor (not set if this
322 * function returns -1.
323 * @return divider which should be used, or -1 if nothing is valid
326 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
327 unsigned long rate, int *extra_div)
330 int best_divider = -1;
331 int best_error = rate;
333 /* try dividers from 1 to 256 and find closest match */
334 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
335 unsigned divided_parent = parent_rate >> shift;
336 int divider = clk_get_divider(divider_bits, divided_parent,
338 unsigned effective_rate = get_rate_from_divider(divided_parent,
340 int error = rate - effective_rate;
342 /* Given a valid divider, look for the lowest error */
343 if (divider != -1 && error < best_error) {
345 *extra_div = 1 << shift;
346 best_divider = divider;
350 /* return what we found - *extra_div will already be set */
355 * Adjust peripheral PLL to use the given divider and source.
357 * @param periph_id peripheral to adjust
358 * @param source Source number (0-3 or 0-7)
359 * @param mux_bits Number of mux bits (2 or 4)
360 * @param divider Required divider in 7.1 or 15.1 format
361 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
362 * for this peripheral)
364 static int adjust_periph_pll(enum periph_id periph_id, int source,
365 int mux_bits, unsigned divider)
367 u32 *reg = get_periph_source_reg(periph_id);
369 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
370 divider << OUT_CLK_DIVISOR_SHIFT);
373 /* work out the source clock and set it */
377 clock_ll_set_source_bits(periph_id, mux_bits, source);
383 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
384 enum clock_id parent, unsigned rate, int *extra_div)
386 unsigned effective_rate;
387 int mux_bits, divider_bits, source;
391 /* work out the source clock and set it */
392 source = get_periph_clock_source(periph_id, parent, &mux_bits,
395 divider = find_best_divider(divider_bits, pll_rate[parent],
400 assert(divider >= 0);
401 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
403 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
404 get_periph_source_reg(periph_id),
405 readl(get_periph_source_reg(periph_id)));
407 /* Check what we ended up with. This shouldn't matter though */
408 effective_rate = clock_get_periph_rate(periph_id, parent);
410 effective_rate /= *extra_div;
411 if (rate != effective_rate)
412 debug("Requested clock rate %u not honored (got %u)\n",
413 rate, effective_rate);
414 return effective_rate;
417 unsigned clock_start_periph_pll(enum periph_id periph_id,
418 enum clock_id parent, unsigned rate)
420 unsigned effective_rate;
422 reset_set_enable(periph_id, 1);
423 clock_enable(periph_id);
425 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
428 reset_set_enable(periph_id, 0);
429 return effective_rate;
432 void clock_enable(enum periph_id clkid)
434 clock_set_enable(clkid, 1);
437 void clock_disable(enum periph_id clkid)
439 clock_set_enable(clkid, 0);
442 void reset_periph(enum periph_id periph_id, int us_delay)
444 /* Put peripheral into reset */
445 reset_set_enable(periph_id, 1);
449 reset_set_enable(periph_id, 0);
454 void reset_cmplx_set_enable(int cpu, int which, int reset)
456 struct clk_rst_ctlr *clkrst =
457 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
460 /* Form the mask, which depends on the cpu chosen (2 or 4) */
461 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
464 /* either enable or disable those reset for that CPU */
466 writel(mask, &clkrst->crc_cpu_cmplx_set);
468 writel(mask, &clkrst->crc_cpu_cmplx_clr);
471 unsigned clock_get_rate(enum clock_id clkid)
479 parent_rate = osc_freq[clock_get_osc_freq()];
480 if (clkid == CLOCK_ID_OSC)
483 pll = get_pll(clkid);
486 base = readl(&pll->pll_base);
488 /* Oh for bf_unpack()... */
489 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
490 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
491 if (clkid == CLOCK_ID_USB)
492 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
494 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
500 * Set the output frequency you want for each PLL clock.
501 * PLL output frequencies are programmed by setting their N, M and P values.
502 * The governing equations are:
503 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
504 * where Fo is the output frequency from the PLL.
505 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
506 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
507 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
509 * @param n PLL feedback divider(DIVN)
510 * @param m PLL input divider(DIVN)
511 * @param p post divider(DIVP)
512 * @param cpcon base PLL charge pump(CPCON)
513 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
514 * be overriden), 1 if PLL is already correct
516 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
522 pll = get_pll(clkid);
524 base_reg = readl(&pll->pll_base);
526 /* Set BYPASS, m, n and p to PLL_BASE */
527 base_reg &= ~PLL_DIVM_MASK;
528 base_reg |= m << PLL_DIVM_SHIFT;
530 base_reg &= ~PLL_DIVN_MASK;
531 base_reg |= n << PLL_DIVN_SHIFT;
533 base_reg &= ~PLL_DIVP_MASK;
534 base_reg |= p << PLL_DIVP_SHIFT;
536 if (clkid == CLOCK_ID_PERIPH) {
538 * If the PLL is already set up, check that it is correct
539 * and record this info for clock_verify() to check.
541 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
542 base_reg |= PLL_ENABLE_MASK;
543 if (base_reg != readl(&pll->pll_base))
545 return pllp_valid ? 1 : -1;
547 base_reg |= PLL_BASE_OVRRIDE_MASK;
550 base_reg |= PLL_BYPASS_MASK;
551 writel(base_reg, &pll->pll_base);
553 /* Set cpcon to PLL_MISC */
554 misc_reg = readl(&pll->pll_misc);
555 #if !defined(CONFIG_TEGRA210)
556 misc_reg &= ~PLL_CPCON_MASK;
557 misc_reg |= cpcon << PLL_CPCON_SHIFT;
559 /* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */
560 misc_reg &= ~PLLU_KCP_MASK;
561 misc_reg |= cpcon << PLLU_KCP_SHIFT;
564 writel(misc_reg, &pll->pll_misc);
567 base_reg |= PLL_ENABLE_MASK;
568 writel(base_reg, &pll->pll_base);
571 base_reg &= ~PLL_BYPASS_MASK;
572 writel(base_reg, &pll->pll_base);
577 void clock_ll_start_uart(enum periph_id periph_id)
579 /* Assert UART reset and enable clock */
580 reset_set_enable(periph_id, 1);
581 clock_enable(periph_id);
582 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
587 /* De-assert reset to UART */
588 reset_set_enable(periph_id, 0);
591 #ifdef CONFIG_OF_CONTROL
592 int clock_decode_periph_id(const void *blob, int node)
598 err = fdtdec_get_int_array(blob, node, "clocks", cell,
602 id = clk_id_to_periph_id(cell[1]);
603 assert(clock_periph_id_isvalid(id));
606 #endif /* CONFIG_OF_CONTROL */
608 int clock_verify(void)
610 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
611 u32 reg = readl(&pll->pll_base);
614 printf("Warning: PLLP %x is not correct\n", reg);
617 debug("PLLP %x is correct\n", reg);
621 void clock_init(void)
623 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
624 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
625 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
626 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
627 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
628 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
629 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
630 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
631 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
632 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
633 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
634 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
635 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
638 static void set_avp_clock_source(u32 src)
640 struct clk_rst_ctlr *clkrst =
641 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
644 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
645 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
646 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
647 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
648 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
649 writel(val, &clkrst->crc_sclk_brst_pol);
654 * This function is useful on Tegra30, and any later SoCs that have compatible
655 * PLLP configuration registers.
656 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
658 void tegra30_set_up_pllp(void)
660 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
664 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
665 * run up to 275MHz. On power on, the default sytem clock source is set
666 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
667 * 408MHz which is beyond system clock's upper limit.
669 * The fix is to set the system clock to CLK_M before initializing PLLP,
670 * and then switch back to PLLP_OUT4, which has an appropriate divider
671 * configured, after PLLP has been configured
673 set_avp_clock_source(SCLK_SOURCE_CLKM);
676 * PLLP output frequency set to 408Mhz
677 * PLLC output frequency set to 228Mhz
679 switch (clock_get_osc_freq()) {
680 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
681 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
682 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
685 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
686 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
687 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
690 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
691 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
692 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
694 case CLOCK_OSC_FREQ_19_2:
697 * These are not supported. It is too early to print a
698 * message and the UART likely won't work anyway due to the
699 * oscillator being wrong.
704 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
707 /* Assert RSTN before enable */
708 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
709 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
710 /* Set divisor and reenable */
711 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
712 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
713 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
714 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
715 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
718 /* Assert RSTN before enable */
719 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
720 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
721 /* Set divisor and reenable */
722 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
723 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
724 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
725 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
726 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
728 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
731 int clock_external_output(int clk_id)
733 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
735 if (clk_id >= 1 && clk_id <= 3) {
736 setbits_le32(&pmc->pmc_clk_out_cntrl,
737 1 << (2 + (clk_id - 1) * 8));
739 printf("%s: Unknown output clock id %d\n", __func__, clk_id);