2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gp_padctrl.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/pmc.h>
25 #include <asm/arch-tegra/scu.h>
28 int get_num_cpus(void)
30 struct apb_misc_gp_ctlr *gp;
32 debug("%s entry\n", __func__);
34 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
35 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
52 * Timing tables for each SOC for all four oscillator options.
54 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
58 * Register Field Bits Width
59 * ------------------------------
61 * PLLX_BASE n 17: 8 10
63 * PLLX_MISC cpcon 11: 8 4
66 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
67 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
68 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
69 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
74 * Register Field Bits Width
75 * ------------------------------
77 * PLLX_BASE n 17: 8 10
79 * PLLX_MISC cpcon 11: 8 4
82 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
83 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
84 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
85 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
90 * Register Field Bits Width
91 * ------------------------------
93 * PLLX_BASE n 17: 8 10
95 * PLLX_MISC cpcon 11: 8 4
98 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
99 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
100 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
101 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
106 * Register Field Bits Width
107 * ------------------------------
108 * PLLX_BASE p 23:20 4
109 * PLLX_BASE n 15: 8 8
113 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
114 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
115 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
116 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
122 * Register Field Bits Width
123 * ------------------------------
124 * PLLX_BASE p 23:20 4
125 * PLLX_BASE n 15: 8 8
129 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
130 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
131 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
132 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
138 * Register Field Bits Width
139 * ------------------------------
140 * PLLX_BASE p 24:20 5
141 * PLLX_BASE n 15: 8 8
145 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
146 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
147 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
148 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
152 static inline void pllx_set_iddq(void)
154 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
155 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
157 debug("%s entry\n", __func__);
160 reg = readl(&clkrst->crc_pllx_misc3);
161 reg &= ~PLLX_IDDQ_MASK;
162 writel(reg, &clkrst->crc_pllx_misc3);
164 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
165 readl(&clkrst->crc_pllx_misc3));
169 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
172 int chip = tegra_get_chip();
174 debug("%s entry\n", __func__);
176 /* If PLLX is already enabled, just return */
177 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
178 debug("%s: PLLX already enabled, returning\n", __func__);
184 /* Set BYPASS, m, n and p to PLLX_BASE */
185 reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
186 reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
187 writel(reg, &pll->pll_base);
189 /* Set cpcon to PLLX_MISC */
190 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
191 reg = (cpcon << PLL_CPCON_SHIFT);
195 /* Set dccon to PLLX_MISC if freq > 600MHz */
197 reg |= (1 << PLL_DCCON_SHIFT);
198 writel(reg, &pll->pll_misc);
201 reg = readl(&pll->pll_base);
202 reg &= ~PLL_BYPASS_MASK;
203 writel(reg, &pll->pll_base);
204 debug("%s: base = 0x%08X\n", __func__, reg);
206 /* Set lock_enable to PLLX_MISC */
207 reg = readl(&pll->pll_misc);
208 reg |= PLL_LOCK_ENABLE_MASK;
209 writel(reg, &pll->pll_misc);
210 debug("%s: misc = 0x%08X\n", __func__, reg);
212 /* Enable PLLX last, once it's all configured */
213 reg = readl(&pll->pll_base);
214 reg |= PLL_ENABLE_MASK;
215 writel(reg, &pll->pll_base);
216 debug("%s: base final = 0x%08X\n", __func__, reg);
223 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
224 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
225 int soc_type, sku_info, chip_sku;
226 enum clock_osc_freq osc;
227 struct clk_pll_table *sel;
228 debug("%s entry\n", __func__);
230 /* get SOC (chip) type */
231 soc_type = tegra_get_chip();
232 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
235 sku_info = tegra_get_sku_info();
236 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
238 /* get chip SKU, combo of the above info */
239 chip_sku = tegra_get_chip_sku();
240 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
243 osc = clock_get_osc_freq();
244 debug("%s: osc = %d\n", __func__, osc);
247 sel = &tegra_pll_x_table[chip_sku][osc];
248 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
251 void enable_cpu_clock(int enable)
253 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
255 debug("%s entry\n", __func__);
259 * Regardless of whether the request is to enable or disable the CPU
260 * clock, every processor in the CPU complex except the master (CPU 0)
261 * will have it's clock stopped because the AVP only talks to the
266 /* Initialize PLLX */
269 /* Wait until all clocks are stable */
270 udelay(PLL_STABILIZATION_DELAY);
272 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
273 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
277 * Read the register containing the individual CPU clock enables and
278 * always stop the clocks to CPUs > 0.
280 clk = readl(&clkrst->crc_clk_cpu_cmplx);
281 clk |= 1 << CPU1_CLK_STP_SHIFT;
282 if (get_num_cpus() == 4)
283 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
285 /* Stop/Unstop the CPU clock */
286 clk &= ~CPU0_CLK_STP_MASK;
287 clk |= !enable << CPU0_CLK_STP_SHIFT;
288 writel(clk, &clkrst->crc_clk_cpu_cmplx);
290 clock_enable(PERIPH_ID_CPU);
293 static int is_cpu_powered(void)
295 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
297 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
300 static void remove_cpu_io_clamps(void)
302 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
304 debug("%s entry\n", __func__);
306 /* Remove the clamps on the CPU I/O signals */
307 reg = readl(&pmc->pmc_remove_clamping);
309 writel(reg, &pmc->pmc_remove_clamping);
311 /* Give I/O signals time to stabilize */
312 udelay(IO_STABILIZATION_DELAY);
315 void powerup_cpu(void)
317 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
319 int timeout = IO_STABILIZATION_DELAY;
320 debug("%s entry\n", __func__);
322 if (!is_cpu_powered()) {
323 /* Toggle the CPU power state (OFF -> ON) */
324 reg = readl(&pmc->pmc_pwrgate_toggle);
327 writel(reg, &pmc->pmc_pwrgate_toggle);
329 /* Wait for the power to come up */
330 while (!is_cpu_powered()) {
332 printf("CPU failed to power up!\n");
338 * Remove the I/O clamps from CPU power partition.
339 * Recommended only on a Warm boot, if the CPU partition gets
340 * power gated. Shouldn't cause any harm when called after a
341 * cold boot according to HW, probably just redundant.
343 remove_cpu_io_clamps();
347 void reset_A9_cpu(int reset)
350 * NOTE: Regardless of whether the request is to hold the CPU in reset
351 * or take it out of reset, every processor in the CPU complex
352 * except the master (CPU 0) will be held in reset because the
353 * AVP only talks to the master. The AVP does not know that there
354 * are multiple processors in the CPU complex.
356 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
357 int num_cpus = get_num_cpus();
360 debug("%s entry\n", __func__);
361 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
362 for (cpu = 1; cpu < num_cpus; cpu++)
363 reset_cmplx_set_enable(cpu, mask, 1);
364 reset_cmplx_set_enable(0, mask, reset);
366 /* Enable/Disable master CPU reset */
367 reset_set_enable(PERIPH_ID_CPU, reset);
370 void clock_enable_coresight(int enable)
374 debug("%s entry\n", __func__);
375 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
376 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
380 * Put CoreSight on PLLP_OUT0 and divide it down as per
381 * PLLP base frequency based on SoC type (T20/T30+).
382 * Clock divider request would setup CSITE clock as 144MHz
383 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
385 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
386 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
388 /* Unlock the CPU CoreSight interfaces */
389 rst = CORESIGHT_UNLOCK;
390 writel(rst, CSITE_CPU_DBG0_LAR);
391 writel(rst, CSITE_CPU_DBG1_LAR);
392 if (get_num_cpus() == 4) {
393 writel(rst, CSITE_CPU_DBG2_LAR);
394 writel(rst, CSITE_CPU_DBG3_LAR);
401 debug("%s entry\n", __func__);
404 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
405 FLOW_CTLR_HALT_COP_EVENTS);