2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 /* Tegra vpr routines */
11 #include <asm/arch/tegra.h>
12 #include <asm/arch/mc.h>
14 #include <fdt_support.h>
16 static bool _configured;
18 void tegra_gpu_config(void)
20 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
23 writel(0, &mc->mc_video_protect_size_mb);
24 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
25 &mc->mc_video_protect_reg_ctrl);
26 /* read back to ensure the write went through */
27 readl(&mc->mc_video_protect_reg_ctrl);
29 debug("configured VPR\n");
34 #if defined(CONFIG_OF_LIBFDT)
36 int tegra_gpu_enable_node(void *blob, const char *compat)
43 offset = fdt_node_offset_by_compatible(blob, -1, compat);
44 while (offset != -FDT_ERR_NOTFOUND) {
45 fdt_status_okay(blob, offset);
46 offset = fdt_node_offset_by_compatible(blob, offset, compat);