2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
19 /* return 1 if a pin_pupd_is in range */
20 #define pmux_pin_pupd_isvalid(pupd) \
21 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
23 /* return 1 if a pin_tristate_is in range */
24 #define pmux_pin_tristate_isvalid(tristate) \
25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
27 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
28 /* return 1 if a pin_io_is in range */
29 #define pmux_pin_io_isvalid(io) \
30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
33 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
34 /* return 1 if a pin_lock is in range */
35 #define pmux_pin_lock_isvalid(lock) \
36 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
39 #ifdef TEGRA_PMX_PINS_HAVE_OD
40 /* return 1 if a pin_od is in range */
41 #define pmux_pin_od_isvalid(od) \
42 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
45 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
46 /* return 1 if a pin_ioreset_is in range */
47 #define pmux_pin_ioreset_isvalid(ioreset) \
48 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
49 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
52 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
53 /* return 1 if a pin_rcv_sel_is in range */
54 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
55 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
56 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
59 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
60 #define pmux_lpmd_isvalid(lpm) \
61 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
64 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
65 #define pmux_schmt_isvalid(schmt) \
66 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
69 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
70 #define pmux_hsm_isvalid(hsm) \
71 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
74 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
76 #if defined(CONFIG_TEGRA20)
78 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
79 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
81 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
82 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
84 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
85 #define TRI_SHIFT(grp) ((grp) % 32)
89 #define REG(pin) _R(0x3000 + ((pin) * 4))
91 #define MUX_REG(pin) REG(pin)
92 #define MUX_SHIFT(pin) 0
94 #define PULL_REG(pin) REG(pin)
95 #define PULL_SHIFT(pin) 2
97 #define TRI_REG(pin) REG(pin)
98 #define TRI_SHIFT(pin) 4
100 #endif /* CONFIG_TEGRA20 */
102 #define DRV_REG(group) _R(0x868 + ((group) * 4))
105 * We could force arch-tegraNN/pinmux.h to define all of these. However,
106 * that's a lot of defines, and for now it's manageable to just put a
107 * special case here. It's possible this decision will change with future
110 #ifdef CONFIG_TEGRA210
118 #define IO_RESET_SHIFT 8
119 #define RCV_SEL_SHIFT 9
122 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
123 /* This register/field only exists on Tegra114 and later */
124 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
125 #define CLAMP_INPUTS_WHEN_TRISTATED 1
127 void pinmux_set_tristate_input_clamping(void)
129 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
131 setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
134 void pinmux_clear_tristate_input_clamping(void)
136 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
138 clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
142 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
144 u32 *reg = MUX_REG(pin);
148 if (func == PMUX_FUNC_DEFAULT)
151 /* Error check on pin and func */
152 assert(pmux_pingrp_isvalid(pin));
153 assert(pmux_func_isvalid(func));
155 if (func >= PMUX_FUNC_RSVD1) {
156 mux = (func - PMUX_FUNC_RSVD1) & 3;
158 /* Search for the appropriate function */
159 for (i = 0; i < 4; i++) {
160 if (tegra_soc_pingroups[pin].funcs[i] == func) {
169 val &= ~(3 << MUX_SHIFT(pin));
170 val |= (mux << MUX_SHIFT(pin));
174 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
176 u32 *reg = PULL_REG(pin);
179 /* Error check on pin and pupd */
180 assert(pmux_pingrp_isvalid(pin));
181 assert(pmux_pin_pupd_isvalid(pupd));
184 val &= ~(3 << PULL_SHIFT(pin));
185 val |= (pupd << PULL_SHIFT(pin));
189 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
191 u32 *reg = TRI_REG(pin);
194 /* Error check on pin */
195 assert(pmux_pingrp_isvalid(pin));
196 assert(pmux_pin_tristate_isvalid(tri));
199 if (tri == PMUX_TRI_TRISTATE)
200 val |= (1 << TRI_SHIFT(pin));
202 val &= ~(1 << TRI_SHIFT(pin));
206 void pinmux_tristate_enable(enum pmux_pingrp pin)
208 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
211 void pinmux_tristate_disable(enum pmux_pingrp pin)
213 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
216 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
217 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
222 if (io == PMUX_PIN_NONE)
225 /* Error check on pin and io */
226 assert(pmux_pingrp_isvalid(pin));
227 assert(pmux_pin_io_isvalid(io));
230 if (io == PMUX_PIN_INPUT)
231 val |= (io & 1) << IO_SHIFT;
233 val &= ~(1 << IO_SHIFT);
238 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
239 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
244 if (lock == PMUX_PIN_LOCK_DEFAULT)
247 /* Error check on pin and lock */
248 assert(pmux_pingrp_isvalid(pin));
249 assert(pmux_pin_lock_isvalid(lock));
252 if (lock == PMUX_PIN_LOCK_ENABLE) {
253 val |= (1 << LOCK_SHIFT);
255 if (val & (1 << LOCK_SHIFT))
256 printf("%s: Cannot clear LOCK bit!\n", __func__);
257 val &= ~(1 << LOCK_SHIFT);
265 #ifdef TEGRA_PMX_PINS_HAVE_OD
266 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
271 if (od == PMUX_PIN_OD_DEFAULT)
274 /* Error check on pin and od */
275 assert(pmux_pingrp_isvalid(pin));
276 assert(pmux_pin_od_isvalid(od));
279 if (od == PMUX_PIN_OD_ENABLE)
280 val |= (1 << OD_SHIFT);
282 val &= ~(1 << OD_SHIFT);
289 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
290 static void pinmux_set_ioreset(enum pmux_pingrp pin,
291 enum pmux_pin_ioreset ioreset)
296 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
299 /* Error check on pin and ioreset */
300 assert(pmux_pingrp_isvalid(pin));
301 assert(pmux_pin_ioreset_isvalid(ioreset));
304 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
305 val |= (1 << IO_RESET_SHIFT);
307 val &= ~(1 << IO_RESET_SHIFT);
314 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
315 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
316 enum pmux_pin_rcv_sel rcv_sel)
321 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
324 /* Error check on pin and rcv_sel */
325 assert(pmux_pingrp_isvalid(pin));
326 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
329 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
330 val |= (1 << RCV_SEL_SHIFT);
332 val &= ~(1 << RCV_SEL_SHIFT);
339 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
341 enum pmux_pingrp pin = config->pingrp;
343 pinmux_set_func(pin, config->func);
344 pinmux_set_pullupdown(pin, config->pull);
345 pinmux_set_tristate(pin, config->tristate);
346 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
347 pinmux_set_io(pin, config->io);
349 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
350 pinmux_set_lock(pin, config->lock);
352 #ifdef TEGRA_PMX_PINS_HAVE_OD
353 pinmux_set_od(pin, config->od);
355 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
356 pinmux_set_ioreset(pin, config->ioreset);
358 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
359 pinmux_set_rcv_sel(pin, config->rcv_sel);
363 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
368 for (i = 0; i < len; i++)
369 pinmux_config_pingrp(&config[i]);
372 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
374 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
376 #define pmux_slw_isvalid(slw) \
377 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
379 #define pmux_drv_isvalid(drv) \
380 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
382 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
385 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
386 #define SCHMT_SHIFT 3
388 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
390 #define LPMD_MASK (3 << LPMD_SHIFT)
393 * Note that the following DRV* and SLW* defines are accurate for many drive
394 * groups on many SoCs. We really need a per-group data structure to solve
395 * this, since the fields are in different positions/sizes in different
396 * registers (for different groups).
398 * On Tegra30/114/124, the DRV*_SHIFT values vary.
399 * On Tegra30, the SLW*_SHIFT values vary.
400 * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
401 * below are wide enough to cover the widest fields, and hopefully don't
402 * interfere with any other fields.
403 * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
404 * wide enough to cover all cases, since that would cause the field to
405 * overlap with other fields in the narrower cases.
407 #define DRVDN_SHIFT 12
408 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
409 #define DRVUP_SHIFT 20
410 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
411 #define SLWR_SHIFT 28
412 #define SLWR_MASK (3 << SLWR_SHIFT)
413 #define SLWF_SHIFT 30
414 #define SLWF_MASK (3 << SLWF_SHIFT)
416 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
418 u32 *reg = DRV_REG(grp);
421 /* NONE means unspecified/do not change/use POR value */
422 if (slwf == PMUX_SLWF_NONE)
425 /* Error check on pad and slwf */
426 assert(pmux_drvgrp_isvalid(grp));
427 assert(pmux_slw_isvalid(slwf));
431 val |= (slwf << SLWF_SHIFT);
437 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
439 u32 *reg = DRV_REG(grp);
442 /* NONE means unspecified/do not change/use POR value */
443 if (slwr == PMUX_SLWR_NONE)
446 /* Error check on pad and slwr */
447 assert(pmux_drvgrp_isvalid(grp));
448 assert(pmux_slw_isvalid(slwr));
452 val |= (slwr << SLWR_SHIFT);
458 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
460 u32 *reg = DRV_REG(grp);
463 /* NONE means unspecified/do not change/use POR value */
464 if (drvup == PMUX_DRVUP_NONE)
467 /* Error check on pad and drvup */
468 assert(pmux_drvgrp_isvalid(grp));
469 assert(pmux_drv_isvalid(drvup));
473 val |= (drvup << DRVUP_SHIFT);
479 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
481 u32 *reg = DRV_REG(grp);
484 /* NONE means unspecified/do not change/use POR value */
485 if (drvdn == PMUX_DRVDN_NONE)
488 /* Error check on pad and drvdn */
489 assert(pmux_drvgrp_isvalid(grp));
490 assert(pmux_drv_isvalid(drvdn));
494 val |= (drvdn << DRVDN_SHIFT);
500 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
501 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
503 u32 *reg = DRV_REG(grp);
506 /* NONE means unspecified/do not change/use POR value */
507 if (lpmd == PMUX_LPMD_NONE)
510 /* Error check pad and lpmd value */
511 assert(pmux_drvgrp_isvalid(grp));
512 assert(pmux_lpmd_isvalid(lpmd));
516 val |= (lpmd << LPMD_SHIFT);
523 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
524 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
526 u32 *reg = DRV_REG(grp);
529 /* NONE means unspecified/do not change/use POR value */
530 if (schmt == PMUX_SCHMT_NONE)
533 /* Error check pad */
534 assert(pmux_drvgrp_isvalid(grp));
535 assert(pmux_schmt_isvalid(schmt));
538 if (schmt == PMUX_SCHMT_ENABLE)
539 val |= (1 << SCHMT_SHIFT);
541 val &= ~(1 << SCHMT_SHIFT);
548 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
549 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
551 u32 *reg = DRV_REG(grp);
554 /* NONE means unspecified/do not change/use POR value */
555 if (hsm == PMUX_HSM_NONE)
558 /* Error check pad */
559 assert(pmux_drvgrp_isvalid(grp));
560 assert(pmux_hsm_isvalid(hsm));
563 if (hsm == PMUX_HSM_ENABLE)
564 val |= (1 << HSM_SHIFT);
566 val &= ~(1 << HSM_SHIFT);
573 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
575 enum pmux_drvgrp grp = config->drvgrp;
577 pinmux_set_drvup_slwf(grp, config->slwf);
578 pinmux_set_drvdn_slwr(grp, config->slwr);
579 pinmux_set_drvup(grp, config->drvup);
580 pinmux_set_drvdn(grp, config->drvdn);
581 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
582 pinmux_set_lpmd(grp, config->lpmd);
584 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
585 pinmux_set_schmt(grp, config->schmt);
587 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
588 pinmux_set_hsm(grp, config->hsm);
592 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
597 for (i = 0; i < len; i++)
598 pinmux_config_drvgrp(&config[i]);
600 #endif /* TEGRA_PMX_HAS_DRVGRPS */