2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
19 /* return 1 if a pin_pupd_is in range */
20 #define pmux_pin_pupd_isvalid(pupd) \
21 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
23 /* return 1 if a pin_tristate_is in range */
24 #define pmux_pin_tristate_isvalid(tristate) \
25 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
27 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
28 /* return 1 if a pin_io_is in range */
29 #define pmux_pin_io_isvalid(io) \
30 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
33 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
34 /* return 1 if a pin_lock is in range */
35 #define pmux_pin_lock_isvalid(lock) \
36 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
39 #ifdef TEGRA_PMX_PINS_HAVE_OD
40 /* return 1 if a pin_od is in range */
41 #define pmux_pin_od_isvalid(od) \
42 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
45 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
46 /* return 1 if a pin_ioreset_is in range */
47 #define pmux_pin_ioreset_isvalid(ioreset) \
48 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
49 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
52 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
53 /* return 1 if a pin_rcv_sel_is in range */
54 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
55 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
56 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
59 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
60 #define pmux_lpmd_isvalid(lpm) \
61 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
64 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
65 #define pmux_schmt_isvalid(schmt) \
66 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
69 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
70 #define pmux_hsm_isvalid(hsm) \
71 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
74 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
76 #if defined(CONFIG_TEGRA20)
78 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
79 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
81 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
82 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
84 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
85 #define TRI_SHIFT(grp) ((grp) % 32)
89 #define REG(pin) _R(0x3000 + ((pin) * 4))
91 #define MUX_REG(pin) REG(pin)
92 #define MUX_SHIFT(pin) 0
94 #define PULL_REG(pin) REG(pin)
95 #define PULL_SHIFT(pin) 2
97 #define TRI_REG(pin) REG(pin)
98 #define TRI_SHIFT(pin) 4
100 #endif /* CONFIG_TEGRA20 */
102 #define DRV_REG(group) _R(0x868 + ((group) * 4))
107 #define IO_RESET_SHIFT 8
108 #define RCV_SEL_SHIFT 9
110 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
111 /* This register/field only exists on Tegra114 and later */
112 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
113 #define CLAMP_INPUTS_WHEN_TRISTATED 1
115 void pinmux_set_tristate_input_clamping(void)
117 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
119 setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
122 void pinmux_clear_tristate_input_clamping(void)
124 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
126 clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
130 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
132 u32 *reg = MUX_REG(pin);
136 if (func == PMUX_FUNC_DEFAULT)
139 /* Error check on pin and func */
140 assert(pmux_pingrp_isvalid(pin));
141 assert(pmux_func_isvalid(func));
143 if (func >= PMUX_FUNC_RSVD1) {
144 mux = (func - PMUX_FUNC_RSVD1) & 3;
146 /* Search for the appropriate function */
147 for (i = 0; i < 4; i++) {
148 if (tegra_soc_pingroups[pin].funcs[i] == func) {
157 val &= ~(3 << MUX_SHIFT(pin));
158 val |= (mux << MUX_SHIFT(pin));
162 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
164 u32 *reg = PULL_REG(pin);
167 /* Error check on pin and pupd */
168 assert(pmux_pingrp_isvalid(pin));
169 assert(pmux_pin_pupd_isvalid(pupd));
172 val &= ~(3 << PULL_SHIFT(pin));
173 val |= (pupd << PULL_SHIFT(pin));
177 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
179 u32 *reg = TRI_REG(pin);
182 /* Error check on pin */
183 assert(pmux_pingrp_isvalid(pin));
184 assert(pmux_pin_tristate_isvalid(tri));
187 if (tri == PMUX_TRI_TRISTATE)
188 val |= (1 << TRI_SHIFT(pin));
190 val &= ~(1 << TRI_SHIFT(pin));
194 void pinmux_tristate_enable(enum pmux_pingrp pin)
196 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
199 void pinmux_tristate_disable(enum pmux_pingrp pin)
201 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
204 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
205 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
210 if (io == PMUX_PIN_NONE)
213 /* Error check on pin and io */
214 assert(pmux_pingrp_isvalid(pin));
215 assert(pmux_pin_io_isvalid(io));
218 if (io == PMUX_PIN_INPUT)
219 val |= (io & 1) << IO_SHIFT;
221 val &= ~(1 << IO_SHIFT);
226 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
227 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
232 if (lock == PMUX_PIN_LOCK_DEFAULT)
235 /* Error check on pin and lock */
236 assert(pmux_pingrp_isvalid(pin));
237 assert(pmux_pin_lock_isvalid(lock));
240 if (lock == PMUX_PIN_LOCK_ENABLE) {
241 val |= (1 << LOCK_SHIFT);
243 if (val & (1 << LOCK_SHIFT))
244 printf("%s: Cannot clear LOCK bit!\n", __func__);
245 val &= ~(1 << LOCK_SHIFT);
253 #ifdef TEGRA_PMX_PINS_HAVE_OD
254 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
259 if (od == PMUX_PIN_OD_DEFAULT)
262 /* Error check on pin and od */
263 assert(pmux_pingrp_isvalid(pin));
264 assert(pmux_pin_od_isvalid(od));
267 if (od == PMUX_PIN_OD_ENABLE)
268 val |= (1 << OD_SHIFT);
270 val &= ~(1 << OD_SHIFT);
277 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
278 static void pinmux_set_ioreset(enum pmux_pingrp pin,
279 enum pmux_pin_ioreset ioreset)
284 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
287 /* Error check on pin and ioreset */
288 assert(pmux_pingrp_isvalid(pin));
289 assert(pmux_pin_ioreset_isvalid(ioreset));
292 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
293 val |= (1 << IO_RESET_SHIFT);
295 val &= ~(1 << IO_RESET_SHIFT);
302 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
303 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
304 enum pmux_pin_rcv_sel rcv_sel)
309 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
312 /* Error check on pin and rcv_sel */
313 assert(pmux_pingrp_isvalid(pin));
314 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
317 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
318 val |= (1 << RCV_SEL_SHIFT);
320 val &= ~(1 << RCV_SEL_SHIFT);
327 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
329 enum pmux_pingrp pin = config->pingrp;
331 pinmux_set_func(pin, config->func);
332 pinmux_set_pullupdown(pin, config->pull);
333 pinmux_set_tristate(pin, config->tristate);
334 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
335 pinmux_set_io(pin, config->io);
337 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
338 pinmux_set_lock(pin, config->lock);
340 #ifdef TEGRA_PMX_PINS_HAVE_OD
341 pinmux_set_od(pin, config->od);
343 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
344 pinmux_set_ioreset(pin, config->ioreset);
346 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
347 pinmux_set_rcv_sel(pin, config->rcv_sel);
351 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
356 for (i = 0; i < len; i++)
357 pinmux_config_pingrp(&config[i]);
360 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
362 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
364 #define pmux_slw_isvalid(slw) \
365 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
367 #define pmux_drv_isvalid(drv) \
368 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
370 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
373 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
374 #define SCHMT_SHIFT 3
376 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
378 #define LPMD_MASK (3 << LPMD_SHIFT)
381 * Note that the following DRV* and SLW* defines are accurate for many drive
382 * groups on many SoCs. We really need a per-group data structure to solve
383 * this, since the fields are in different positions/sizes in different
384 * registers (for different groups).
386 * On Tegra30/114/124, the DRV*_SHIFT values vary.
387 * On Tegra30, the SLW*_SHIFT values vary.
388 * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
389 * below are wide enough to cover the widest fields, and hopefully don't
390 * interfere with any other fields.
391 * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
392 * wide enough to cover all cases, since that would cause the field to
393 * overlap with other fields in the narrower cases.
395 #define DRVDN_SHIFT 12
396 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
397 #define DRVUP_SHIFT 20
398 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
399 #define SLWR_SHIFT 28
400 #define SLWR_MASK (3 << SLWR_SHIFT)
401 #define SLWF_SHIFT 30
402 #define SLWF_MASK (3 << SLWF_SHIFT)
404 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
406 u32 *reg = DRV_REG(grp);
409 /* NONE means unspecified/do not change/use POR value */
410 if (slwf == PMUX_SLWF_NONE)
413 /* Error check on pad and slwf */
414 assert(pmux_drvgrp_isvalid(grp));
415 assert(pmux_slw_isvalid(slwf));
419 val |= (slwf << SLWF_SHIFT);
425 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
427 u32 *reg = DRV_REG(grp);
430 /* NONE means unspecified/do not change/use POR value */
431 if (slwr == PMUX_SLWR_NONE)
434 /* Error check on pad and slwr */
435 assert(pmux_drvgrp_isvalid(grp));
436 assert(pmux_slw_isvalid(slwr));
440 val |= (slwr << SLWR_SHIFT);
446 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
448 u32 *reg = DRV_REG(grp);
451 /* NONE means unspecified/do not change/use POR value */
452 if (drvup == PMUX_DRVUP_NONE)
455 /* Error check on pad and drvup */
456 assert(pmux_drvgrp_isvalid(grp));
457 assert(pmux_drv_isvalid(drvup));
461 val |= (drvup << DRVUP_SHIFT);
467 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
469 u32 *reg = DRV_REG(grp);
472 /* NONE means unspecified/do not change/use POR value */
473 if (drvdn == PMUX_DRVDN_NONE)
476 /* Error check on pad and drvdn */
477 assert(pmux_drvgrp_isvalid(grp));
478 assert(pmux_drv_isvalid(drvdn));
482 val |= (drvdn << DRVDN_SHIFT);
488 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
489 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
491 u32 *reg = DRV_REG(grp);
494 /* NONE means unspecified/do not change/use POR value */
495 if (lpmd == PMUX_LPMD_NONE)
498 /* Error check pad and lpmd value */
499 assert(pmux_drvgrp_isvalid(grp));
500 assert(pmux_lpmd_isvalid(lpmd));
504 val |= (lpmd << LPMD_SHIFT);
511 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
512 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
514 u32 *reg = DRV_REG(grp);
517 /* NONE means unspecified/do not change/use POR value */
518 if (schmt == PMUX_SCHMT_NONE)
521 /* Error check pad */
522 assert(pmux_drvgrp_isvalid(grp));
523 assert(pmux_schmt_isvalid(schmt));
526 if (schmt == PMUX_SCHMT_ENABLE)
527 val |= (1 << SCHMT_SHIFT);
529 val &= ~(1 << SCHMT_SHIFT);
536 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
537 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
539 u32 *reg = DRV_REG(grp);
542 /* NONE means unspecified/do not change/use POR value */
543 if (hsm == PMUX_HSM_NONE)
546 /* Error check pad */
547 assert(pmux_drvgrp_isvalid(grp));
548 assert(pmux_hsm_isvalid(hsm));
551 if (hsm == PMUX_HSM_ENABLE)
552 val |= (1 << HSM_SHIFT);
554 val &= ~(1 << HSM_SHIFT);
561 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
563 enum pmux_drvgrp grp = config->drvgrp;
565 pinmux_set_drvup_slwf(grp, config->slwf);
566 pinmux_set_drvdn_slwr(grp, config->slwr);
567 pinmux_set_drvup(grp, config->drvup);
568 pinmux_set_drvdn(grp, config->drvdn);
569 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
570 pinmux_set_lpmd(grp, config->lpmd);
572 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
573 pinmux_set_schmt(grp, config->schmt);
575 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
576 pinmux_set_hsm(grp, config->hsm);
580 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
585 for (i = 0; i < len; i++)
586 pinmux_config_drvgrp(&config[i]);
588 #endif /* TEGRA_PMX_HAS_DRVGRPS */