1 // SPDX-License-Identifier: GPL-2.0+
4 * NVIDIA Corporation <www.nvidia.com>
7 /* Tegra124 high-level function multiplexing */
10 #include <asm/arch/clock.h>
11 #include <asm/arch/funcmux.h>
12 #include <asm/arch/pinmux.h>
14 int funcmux_select(enum periph_id id, int config)
16 int bad_config = config != FUNCMUX_DEFAULT;
21 case FUNCMUX_UART4_GPIO: /* TXD,RXD,CTS,RTS */
22 pinmux_set_func(PMUX_PINGRP_PJ7, PMUX_FUNC_UARTD);
23 pinmux_set_func(PMUX_PINGRP_PB0, PMUX_FUNC_UARTD);
24 pinmux_set_func(PMUX_PINGRP_PB1, PMUX_FUNC_UARTD);
25 pinmux_set_func(PMUX_PINGRP_PK7, PMUX_FUNC_UARTD);
27 pinmux_set_io(PMUX_PINGRP_PJ7, PMUX_PIN_OUTPUT);
28 pinmux_set_io(PMUX_PINGRP_PB0, PMUX_PIN_INPUT);
29 pinmux_set_io(PMUX_PINGRP_PB1, PMUX_PIN_INPUT);
30 pinmux_set_io(PMUX_PINGRP_PK7, PMUX_PIN_OUTPUT);
32 pinmux_tristate_disable(PMUX_PINGRP_PJ7);
33 pinmux_tristate_disable(PMUX_PINGRP_PB0);
34 pinmux_tristate_disable(PMUX_PINGRP_PB1);
35 pinmux_tristate_disable(PMUX_PINGRP_PK7);
42 case FUNCMUX_UART1_KBC:
43 pinmux_set_func(PMUX_PINGRP_KB_ROW9_PS1,
45 pinmux_set_func(PMUX_PINGRP_KB_ROW10_PS2,
48 pinmux_set_io(PMUX_PINGRP_KB_ROW9_PS1, PMUX_PIN_OUTPUT);
49 pinmux_set_io(PMUX_PINGRP_KB_ROW10_PS2, PMUX_PIN_INPUT);
51 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW9_PS1);
52 pinmux_tristate_disable(PMUX_PINGRP_KB_ROW10_PS2);
57 /* Add other periph IDs here as needed */
60 debug("%s: invalid periph_id %d", __func__, id);
65 debug("%s: invalid config %d for periph_id %d", __func__,