2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
16 #include <asm/arch/clock.h>
17 #include <asm/arch-tegra/xusb-padctl.h>
19 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
21 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
22 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
23 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
24 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
26 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
27 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
32 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
36 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
37 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
43 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
44 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
45 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
47 enum tegra124_function {
57 static const char *const tegra124_functions[] = {
67 static const unsigned int tegra124_otg_functions[] = {
74 static const unsigned int tegra124_usb_functions[] = {
79 static const unsigned int tegra124_pci_functions[] = {
86 struct tegra_xusb_padctl_lane {
94 const unsigned int *funcs;
95 unsigned int num_funcs;
98 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
105 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
106 .funcs = tegra124_##_funcs##_functions, \
109 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
110 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
111 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
112 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
113 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
114 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
115 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
116 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
117 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
118 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
119 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
120 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
121 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
124 struct tegra_xusb_phy_ops {
125 int (*prepare)(struct tegra_xusb_phy *phy);
126 int (*enable)(struct tegra_xusb_phy *phy);
127 int (*disable)(struct tegra_xusb_phy *phy);
128 int (*unprepare)(struct tegra_xusb_phy *phy);
131 struct tegra_xusb_phy {
132 const struct tegra_xusb_phy_ops *ops;
134 struct tegra_xusb_padctl *padctl;
137 struct tegra_xusb_padctl_pin {
138 const struct tegra_xusb_padctl_lane *lane;
147 struct tegra_xusb_padctl_group {
150 const char *pins[MAX_PINS];
151 unsigned int num_pins;
157 struct tegra_xusb_padctl_config {
160 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
161 unsigned int num_groups;
164 struct tegra_xusb_padctl {
165 struct fdt_resource regs;
169 struct tegra_xusb_phy phys[2];
171 const struct tegra_xusb_padctl_lane *lanes;
172 unsigned int num_lanes;
174 const char *const *functions;
175 unsigned int num_functions;
177 struct tegra_xusb_padctl_config config;
180 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
181 unsigned long offset)
183 return readl(padctl->regs.start + offset);
186 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
187 u32 value, unsigned long offset)
189 writel(value, padctl->regs.start + offset);
192 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
196 if (padctl->enable++ > 0)
199 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
200 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
201 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
205 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
206 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
207 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
211 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
212 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
213 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
218 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
222 if (padctl->enable == 0) {
223 error("tegra-xusb-padctl: unbalanced enable/disable");
227 if (--padctl->enable > 0)
230 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
231 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
232 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
236 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
237 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
238 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
242 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
243 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
244 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
249 static int phy_prepare(struct tegra_xusb_phy *phy)
251 return tegra_xusb_padctl_enable(phy->padctl);
254 static int phy_unprepare(struct tegra_xusb_phy *phy)
256 return tegra_xusb_padctl_disable(phy->padctl);
259 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
261 struct tegra_xusb_padctl *padctl = phy->padctl;
262 int err = -ETIMEDOUT;
266 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
267 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
268 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
270 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
271 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
272 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
273 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
274 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
276 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
277 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
278 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
280 start = get_timer(0);
282 while (get_timer(start) < 50) {
283 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
284 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
293 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
295 struct tegra_xusb_padctl *padctl = phy->padctl;
298 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
299 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
300 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
305 static int sata_phy_enable(struct tegra_xusb_phy *phy)
307 struct tegra_xusb_padctl *padctl = phy->padctl;
308 int err = -ETIMEDOUT;
312 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
313 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
314 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
315 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
317 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
318 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
319 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
320 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
322 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
323 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
324 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
326 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
327 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
328 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
330 start = get_timer(0);
332 while (get_timer(start) < 50) {
333 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
334 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
343 static int sata_phy_disable(struct tegra_xusb_phy *phy)
345 struct tegra_xusb_padctl *padctl = phy->padctl;
348 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
349 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
350 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
352 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
353 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
354 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
356 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
357 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
358 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
359 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
361 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
362 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
363 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
364 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
369 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
370 .prepare = phy_prepare,
371 .enable = pcie_phy_enable,
372 .disable = pcie_phy_disable,
373 .unprepare = phy_unprepare,
376 static const struct tegra_xusb_phy_ops sata_phy_ops = {
377 .prepare = phy_prepare,
378 .enable = sata_phy_enable,
379 .disable = sata_phy_disable,
380 .unprepare = phy_unprepare,
383 static struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
386 .ops = &pcie_phy_ops,
389 .ops = &sata_phy_ops,
394 static const struct tegra_xusb_padctl_lane *
395 tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
399 for (i = 0; i < padctl->num_lanes; i++)
400 if (strcmp(name, padctl->lanes[i].name) == 0)
401 return &padctl->lanes[i];
407 tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
408 struct tegra_xusb_padctl_group *group,
409 const void *fdt, int node)
414 group->name = fdt_get_name(fdt, node, &len);
416 len = fdt_count_strings(fdt, node, "nvidia,lanes");
418 error("tegra-xusb-padctl: failed to parse \"nvidia,lanes\" property");
422 group->num_pins = len;
424 for (i = 0; i < group->num_pins; i++) {
425 err = fdt_get_string_index(fdt, node, "nvidia,lanes", i,
428 error("tegra-xusb-padctl: failed to read string from \"nvidia,lanes\" property");
433 group->num_pins = len;
435 err = fdt_get_string(fdt, node, "nvidia,function", &group->func);
437 error("tegra-xusb-padctl: failed to parse \"nvidia,func\" property");
441 group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1);
446 static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
451 for (i = 0; i < padctl->num_functions; i++)
452 if (strcmp(name, padctl->functions[i]) == 0)
459 tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
460 const struct tegra_xusb_padctl_lane *lane,
466 func = tegra_xusb_padctl_find_function(padctl, name);
470 for (i = 0; i < lane->num_funcs; i++)
471 if (lane->funcs[i] == func)
478 tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
479 const struct tegra_xusb_padctl_group *group)
483 for (i = 0; i < group->num_pins; i++) {
484 const struct tegra_xusb_padctl_lane *lane;
488 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
490 error("tegra-xusb-padctl: no lane for pin %s",
495 func = tegra_xusb_padctl_lane_find_function(padctl, lane,
498 error("tegra-xusb-padctl: function %s invalid for lane %s: %d",
499 group->func, lane->name, func);
503 value = padctl_readl(padctl, lane->offset);
505 /* set pin function */
506 value &= ~(lane->mask << lane->shift);
507 value |= func << lane->shift;
510 * Set IDDQ if supported on the lane and specified in the
513 if (lane->iddq > 0 && group->iddq >= 0) {
514 if (group->iddq != 0)
515 value &= ~(1 << lane->iddq);
517 value |= 1 << lane->iddq;
520 padctl_writel(padctl, value, lane->offset);
527 tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
528 struct tegra_xusb_padctl_config *config)
532 for (i = 0; i < config->num_groups; i++) {
533 const struct tegra_xusb_padctl_group *group;
536 group = &config->groups[i];
538 err = tegra_xusb_padctl_group_apply(padctl, group);
540 error("tegra-xusb-padctl: failed to apply group %s: %d",
550 tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
551 struct tegra_xusb_padctl_config *config,
552 const void *fdt, int node)
556 config->name = fdt_get_name(fdt, node, NULL);
558 fdt_for_each_subnode(fdt, subnode, node) {
559 struct tegra_xusb_padctl_group *group;
562 group = &config->groups[config->num_groups];
564 err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt,
567 error("tegra-xusb-padctl: failed to parse group %s",
572 config->num_groups++;
578 static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
579 const void *fdt, int node)
583 err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs);
585 error("tegra-xusb-padctl: registers not found");
589 fdt_for_each_subnode(fdt, subnode, node) {
590 struct tegra_xusb_padctl_config *config = &padctl->config;
592 err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt,
595 error("tegra-xusb-padctl: failed to parse entry %s: %d",
604 static int process_nodes(const void *fdt, int nodes[], unsigned int count)
608 for (i = 0; i < count; i++) {
609 enum fdt_compat_id id;
612 if (!fdtdec_get_is_enabled(fdt, nodes[i]))
615 id = fdtdec_lookup(fdt, nodes[i]);
617 case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
621 error("tegra-xusb-padctl: unsupported compatible: %s",
622 fdtdec_get_compatible(id));
626 padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
627 padctl->lanes = tegra124_lanes;
629 padctl->num_functions = ARRAY_SIZE(tegra124_functions);
630 padctl->functions = tegra124_functions;
632 err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
634 error("tegra-xusb-padctl: failed to parse DT: %d",
639 /* deassert XUSB padctl reset */
640 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
642 err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
644 error("tegra-xusb-padctl: failed to apply pinmux: %d",
649 /* only a single instance is supported */
656 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
658 struct tegra_xusb_phy *phy = NULL;
661 case TEGRA_XUSB_PADCTL_PCIE:
662 phy = &padctl->phys[0];
663 phy->padctl = padctl;
666 case TEGRA_XUSB_PADCTL_SATA:
667 phy = &padctl->phys[1];
668 phy->padctl = padctl;
675 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
677 if (phy && phy->ops && phy->ops->prepare)
678 return phy->ops->prepare(phy);
680 return phy ? -ENOSYS : -EINVAL;
683 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
685 if (phy && phy->ops && phy->ops->enable)
686 return phy->ops->enable(phy);
688 return phy ? -ENOSYS : -EINVAL;
691 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
693 if (phy && phy->ops && phy->ops->disable)
694 return phy->ops->disable(phy);
696 return phy ? -ENOSYS : -EINVAL;
699 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
701 if (phy && phy->ops && phy->ops->unprepare)
702 return phy->ops->unprepare(phy);
704 return phy ? -ENOSYS : -EINVAL;
707 void tegra_xusb_padctl_init(const void *fdt)
711 count = fdtdec_find_aliases_for_id(fdt, "padctl",
712 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
713 nodes, ARRAY_SIZE(nodes));
714 if (process_nodes(fdt, nodes, count))