2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
14 #include "../xusb-padctl-common.h"
18 #include <asm/arch/clock.h>
19 #include <asm/arch-tegra/xusb-padctl.h>
21 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #define XUSB_PADCTL_ELPG_PROGRAM 0x01c
24 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
25 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
26 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
28 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1 0x040
29 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
30 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK (0xf << 12)
31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2 0x044
34 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
35 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL (1 << 4)
38 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1 0x138
39 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET (1 << 27)
40 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE (1 << 24)
41 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD (1 << 3)
42 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST (1 << 1)
43 #define XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ (1 << 0)
45 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1 0x148
46 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD (1 << 1)
47 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ (1 << 0)
49 enum tegra124_function {
59 static const char *const tegra124_functions[] = {
69 static const unsigned int tegra124_otg_functions[] = {
76 static const unsigned int tegra124_usb_functions[] = {
81 static const unsigned int tegra124_pci_functions[] = {
88 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
95 .num_funcs = ARRAY_SIZE(tegra124_##_funcs##_functions), \
96 .funcs = tegra124_##_funcs##_functions, \
99 static const struct tegra_xusb_padctl_lane tegra124_lanes[] = {
100 TEGRA124_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
101 TEGRA124_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
102 TEGRA124_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
103 TEGRA124_LANE("ulpi-0", 0x004, 12, 0x1, 0, usb),
104 TEGRA124_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
105 TEGRA124_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
106 TEGRA124_LANE("pcie-0", 0x134, 16, 0x3, 1, pci),
107 TEGRA124_LANE("pcie-1", 0x134, 18, 0x3, 2, pci),
108 TEGRA124_LANE("pcie-2", 0x134, 20, 0x3, 3, pci),
109 TEGRA124_LANE("pcie-3", 0x134, 22, 0x3, 4, pci),
110 TEGRA124_LANE("pcie-4", 0x134, 24, 0x3, 5, pci),
111 TEGRA124_LANE("sata-0", 0x134, 26, 0x3, 6, pci),
114 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
118 if (padctl->enable++ > 0)
121 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
122 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
123 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
127 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
128 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
129 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
133 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
134 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
135 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
140 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
144 if (padctl->enable == 0) {
145 error("unbalanced enable/disable");
149 if (--padctl->enable > 0)
152 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
153 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
154 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
158 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
159 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
160 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
164 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
165 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
166 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
171 static int phy_prepare(struct tegra_xusb_phy *phy)
173 return tegra_xusb_padctl_enable(phy->padctl);
176 static int phy_unprepare(struct tegra_xusb_phy *phy)
178 return tegra_xusb_padctl_disable(phy->padctl);
181 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
183 struct tegra_xusb_padctl *padctl = phy->padctl;
184 int err = -ETIMEDOUT;
188 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
189 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_REFCLK_SEL_MASK;
190 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
192 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
193 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN |
194 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN |
195 XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_SEL;
196 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL2);
198 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
199 value |= XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
200 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
202 start = get_timer(0);
204 while (get_timer(start) < 50) {
205 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
206 if (value & XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET) {
215 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
217 struct tegra_xusb_padctl *padctl = phy->padctl;
220 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
221 value &= ~XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST;
222 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_P0_CTL1);
227 static int sata_phy_enable(struct tegra_xusb_phy *phy)
229 struct tegra_xusb_padctl *padctl = phy->padctl;
230 int err = -ETIMEDOUT;
234 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
235 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
236 value &= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
237 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
239 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
240 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
241 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
242 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
244 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
245 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
246 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
248 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
249 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
250 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
252 start = get_timer(0);
254 while (get_timer(start) < 50) {
255 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
256 if (value & XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_LOCKDET) {
265 static int sata_phy_disable(struct tegra_xusb_phy *phy)
267 struct tegra_xusb_padctl *padctl = phy->padctl;
270 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
271 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_RST;
272 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
274 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
275 value &= ~XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL1_MODE;
276 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
278 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
279 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_PWR_OVRD;
280 value |= XUSB_PADCTL_IOPHY_PLL_S0_CTL1_PLL_IDDQ;
281 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_PLL_S0_CTL1);
283 value = padctl_readl(padctl, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
284 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ_OVRD;
285 value |= ~XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_IDDQ;
286 padctl_writel(padctl, value, XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1);
291 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
292 .prepare = phy_prepare,
293 .enable = pcie_phy_enable,
294 .disable = pcie_phy_disable,
295 .unprepare = phy_unprepare,
298 static const struct tegra_xusb_phy_ops sata_phy_ops = {
299 .prepare = phy_prepare,
300 .enable = sata_phy_enable,
301 .disable = sata_phy_disable,
302 .unprepare = phy_unprepare,
305 struct tegra_xusb_padctl *padctl = &(struct tegra_xusb_padctl) {
308 .ops = &pcie_phy_ops,
311 .ops = &sata_phy_ops,
316 int process_nodes(const void *fdt, int nodes[], unsigned int count)
320 for (i = 0; i < count; i++) {
321 enum fdt_compat_id id;
324 if (!fdtdec_get_is_enabled(fdt, nodes[i]))
327 id = fdtdec_lookup(fdt, nodes[i]);
329 case COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL:
333 error("unsupported compatible: %s",
334 fdtdec_get_compatible(id));
338 padctl->num_lanes = ARRAY_SIZE(tegra124_lanes);
339 padctl->lanes = tegra124_lanes;
341 padctl->num_functions = ARRAY_SIZE(tegra124_functions);
342 padctl->functions = tegra124_functions;
344 err = tegra_xusb_padctl_parse_dt(padctl, fdt, nodes[i]);
346 error("failed to parse DT: %d", err);
350 /* deassert XUSB padctl reset */
351 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
353 err = tegra_xusb_padctl_config_apply(padctl, &padctl->config);
355 error("failed to apply pinmux: %d", err);
359 /* only a single instance is supported */
366 void tegra_xusb_padctl_init(const void *fdt)
370 count = fdtdec_find_aliases_for_id(fdt, "padctl",
371 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
372 nodes, ARRAY_SIZE(nodes));
373 if (process_nodes(fdt, nodes, count))