2 * Copyright (c) 2016-2018, NVIDIA CORPORATION.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <fdt_support.h>
10 #include <asm/arch/tegra.h>
12 #define SZ_4G 0x100000000ULL
15 * Size of a region that's large enough to hold the relocated U-Boot and all
16 * other allocations made around it (stack, heap, page tables, etc.)
17 * In practice, running "bdinfo" at the shell prompt, the stack reaches about
18 * 5MB from the address selected for ram_top as of the time of writing,
19 * so a 16MB region should be plenty.
21 #define MIN_USABLE_RAM_SIZE SZ_16M
23 * The amount of space we expect to require for stack usage. Used to validate
24 * that all reservations fit into the region selected for the relocation target
26 #define MIN_USABLE_STACK_SIZE SZ_1M
28 DECLARE_GLOBAL_DATA_PTR;
30 extern unsigned long nvtboot_boot_x0;
33 * These variables are written to before relocation, and hence cannot be
34 * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
35 * The section attribute forces this into .data and avoids this issue. This
36 * also has the nice side-effect of the content being valid after relocation.
39 /* A parsed version of /memory/reg from the DTB passed to U-Boot in x0 */
43 } ram_banks[CONFIG_NR_DRAM_BANKS] __attribute__((section(".data")));
45 /* The number of valid entries in ram_banks[] */
46 static int ram_bank_count __attribute__((section(".data")));
49 * The usable top-of-RAM for U-Boot. This is both:
50 * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
51 * b) At the end of a region that has enough space to hold the relocated U-Boot
52 * and all other allocations made around it (stack, heap, page tables, etc.)
54 static u64 ram_top __attribute__((section(".data")));
55 /* The base address of the region of RAM that ends at ram_top */
56 static u64 region_base __attribute__((section(".data")));
61 const void *nvtboot_blob = (void *)nvtboot_boot_x0;
65 memset(ram_banks, 0, sizeof(ram_banks));
67 na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
68 ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
70 node = fdt_path_offset(nvtboot_blob, "/memory");
72 pr_err("Can't find /memory node in nvtboot DTB");
75 prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
77 pr_err("Can't find /memory/reg property in nvtboot DTB");
81 /* Calculate the true # of base/size pairs to read */
82 len /= 4; /* Convert bytes to number of cells */
83 len /= (na + ns); /* Convert cells to number of banks */
84 if (len > ARRAY_SIZE(ram_banks))
85 len = ARRAY_SIZE(ram_banks);
89 for (i = 0; i < ram_bank_count; i++) {
90 u64 bank_end, usable_bank_size;
92 ram_banks[i].start = fdt_read_number(prop, na);
94 ram_banks[i].size = fdt_read_number(prop, ns);
96 gd->ram_size += ram_banks[i].size;
97 debug("Bank %d: start: %llx size: %llx\n", i,
98 ram_banks[i].start, ram_banks[i].size);
100 bank_end = ram_banks[i].start + ram_banks[i].size;
101 debug(" end %llx\n", bank_end);
102 if (bank_end > SZ_4G)
104 debug(" end %llx (usable)\n", bank_end);
105 usable_bank_size = bank_end - ram_banks[i].start;
106 debug(" size %llx (usable)\n", usable_bank_size);
107 if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
108 (bank_end > ram_top)) {
110 region_base = ram_banks[i].start;
111 debug("ram top now %llx\n", ram_top);
115 pr_err("Can't find a usable RAM top");
122 int dram_init_banksize(void)
126 if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
127 pr_err("Reservations exceed chosen region size");
131 for (i = 0; i < ram_bank_count; i++) {
132 gd->bd->bi_dram[i].start = ram_banks[i].start;
133 gd->bd->bi_dram[i].size = ram_banks[i].size;
137 gd->pci_ram_top = ram_top;
143 ulong board_get_usable_ram_top(ulong total_size)