2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra20 Clock control functions */
12 #include <asm/arch/clock.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra20 has muxes for the
21 * peripheral clocks, and in most cases there are four options for the clock
22 * source. This gives us a clock 'type' and exploits what commonality exists
25 * Letters are obvious, except for T which means CLK_M, and S which means the
26 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
27 * datasheet) and PLL_M are different things. The former is the basic
28 * clock supplied to the SOC from an external oscillator. The latter is the
31 * See definitions in clock_id in the header file.
34 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
35 CLOCK_TYPE_MCPA, /* and so on */
39 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
44 CLOCK_TYPE_NONE = -1, /* invalid clock type */
48 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
52 * Clock source mux for each clock type. This just converts our enum into
53 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
54 * is special as it has 5 sources. Since it also has a different number of
55 * bits in its register for the source, we just handle it with a special
58 #define CLK(x) CLOCK_ID_ ## x
59 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
60 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
61 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
62 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
63 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
64 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
65 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
66 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
67 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
71 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
72 * not in the header file since it is for purely internal use - we want
73 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
74 * confusion bewteen PERIPH_ID_... and PERIPHC_...
76 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
79 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
80 * use it for reset, clock enable, clock source/divider and even pinmuxing
83 enum periphc_internal_id {
100 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
158 * Clock type for each peripheral clock source. We put the name in each
159 * record just so it is easy to match things up
161 #define TYPE(name, type) type
162 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
164 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
165 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
166 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
167 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
168 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
169 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
170 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
171 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
174 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
175 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
176 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
177 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
178 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
179 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
180 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
181 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
184 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
185 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
186 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
187 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
188 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
189 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
190 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
191 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
194 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
195 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
196 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
197 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
198 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
199 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
200 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
201 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
204 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
205 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
206 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
207 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
208 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
209 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
210 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
211 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
214 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
215 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
216 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
217 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
220 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
221 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
224 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
225 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
226 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
227 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
229 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
233 * This array translates a periph_id to a periphc_internal_id
235 * Not present/matched up:
236 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
237 * SPDIF - which is both 0x08 and 0x0c
240 #define NONE(name) (-1)
241 #define OFFSET(name, value) PERIPHC_ ## name
242 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
251 PERIPHC_UART2, /* and vfir 0x68 */
256 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
283 /* Middle word: 63:32 */
295 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
305 PERIPHC_TVO, /* also CVE 0x40 */
323 /* Upper word 95:64 */
358 * Get the oscillator frequency, from the corresponding hardware configuration
359 * field. T20 has 4 frequencies that it supports.
361 enum clock_osc_freq clock_get_osc_freq(void)
363 struct clk_rst_ctlr *clkrst =
364 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
367 reg = readl(&clkrst->crc_osc_ctrl);
368 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
371 /* Returns a pointer to the clock source register for a peripheral */
372 u32 *get_periph_source_reg(enum periph_id periph_id)
374 struct clk_rst_ctlr *clkrst =
375 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
376 enum periphc_internal_id internal_id;
378 assert(clock_periph_id_isvalid(periph_id));
379 internal_id = periph_id_to_internal_id[periph_id];
380 assert(internal_id != -1);
381 return &clkrst->crc_clk_src[internal_id];
385 * Given a peripheral ID and the required source clock, this returns which
386 * value should be programmed into the source mux for that peripheral.
388 * There is special code here to handle the one source type with 5 sources.
390 * @param periph_id peripheral to start
391 * @param source PLL id of required parent clock
392 * @param mux_bits Set to number of bits in mux register: 2 or 4
393 * @param divider_bits Set to number of divider bits (8 or 16)
394 * @return mux value (0-4, or -1 if not found)
396 int get_periph_clock_source(enum periph_id periph_id,
397 enum clock_id parent, int *mux_bits, int *divider_bits)
399 enum clock_type_id type;
400 enum periphc_internal_id internal_id;
403 assert(clock_periph_id_isvalid(periph_id));
405 internal_id = periph_id_to_internal_id[periph_id];
406 assert(periphc_internal_id_isvalid(internal_id));
408 type = clock_periph_type[internal_id];
409 assert(clock_type_id_isvalid(type));
412 * Special cases here for the clock with a 4-bit source mux and I2C
413 * with its 16-bit divisor
415 if (type == CLOCK_TYPE_PCXTS)
416 *mux_bits = MASK_BITS_31_28;
418 *mux_bits = MASK_BITS_31_30;
419 if (type == CLOCK_TYPE_PCMT16)
424 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
425 if (clock_source[type][mux] == parent)
429 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
430 * which is not in our table. If not, then they are asking for a
431 * source which this peripheral can't access through its mux.
433 assert(type == CLOCK_TYPE_PCXTS);
434 assert(parent == CLOCK_ID_SFROM32KHZ);
435 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
436 return 4; /* mux value for this clock */
438 /* if we get here, either us or the caller has made a mistake */
439 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
444 void clock_set_enable(enum periph_id periph_id, int enable)
446 struct clk_rst_ctlr *clkrst =
447 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
448 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
451 /* Enable/disable the clock to this peripheral */
452 assert(clock_periph_id_isvalid(periph_id));
455 reg |= PERIPH_MASK(periph_id);
457 reg &= ~PERIPH_MASK(periph_id);
461 void reset_set_enable(enum periph_id periph_id, int enable)
463 struct clk_rst_ctlr *clkrst =
464 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
465 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
468 /* Enable/disable reset to the peripheral */
469 assert(clock_periph_id_isvalid(periph_id));
472 reg |= PERIPH_MASK(periph_id);
474 reg &= ~PERIPH_MASK(periph_id);
478 #ifdef CONFIG_OF_CONTROL
480 * Convert a device tree clock ID to our peripheral ID. They are mostly
481 * the same but we are very cautious so we check that a valid clock ID is
484 * @param clk_id Clock ID according to tegra20 device tree binding
485 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
487 enum periph_id clk_id_to_periph_id(int clk_id)
489 if (clk_id > PERIPH_ID_COUNT)
490 return PERIPH_ID_NONE;
493 case PERIPH_ID_RESERVED1:
494 case PERIPH_ID_RESERVED2:
495 case PERIPH_ID_RESERVED30:
496 case PERIPH_ID_RESERVED35:
497 case PERIPH_ID_RESERVED56:
498 case PERIPH_ID_PCIEXCLK:
499 case PERIPH_ID_RESERVED76:
500 case PERIPH_ID_RESERVED77:
501 case PERIPH_ID_RESERVED78:
502 case PERIPH_ID_RESERVED79:
503 case PERIPH_ID_RESERVED80:
504 case PERIPH_ID_RESERVED81:
505 case PERIPH_ID_RESERVED82:
506 case PERIPH_ID_RESERVED83:
507 case PERIPH_ID_RESERVED91:
508 return PERIPH_ID_NONE;
513 #endif /* CONFIG_OF_CONTROL */
515 void clock_early_init(void)
518 * PLLP output frequency set to 216MHz
519 * PLLC output frequency set to 600Mhz
521 * TODO: Can we calculate these values instead of hard-coding?
523 switch (clock_get_osc_freq()) {
524 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
525 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
526 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
529 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
530 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
531 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
534 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
535 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
536 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
538 case CLOCK_OSC_FREQ_19_2:
541 * These are not supported. It is too early to print a
542 * message and the UART likely won't work anyway due to the
543 * oscillator being wrong.
549 void arch_timer_init(void)
553 #define PMC_SATA_PWRGT 0x1ac
554 #define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
555 #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
557 #define PLLE_SS_CNTL 0x68
558 #define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
559 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
560 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
561 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
562 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
563 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
565 #define PLLE_BASE 0x0e8
566 #define PLLE_BASE_ENABLE_CML (1 << 31)
567 #define PLLE_BASE_ENABLE (1 << 30)
568 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
569 #define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
570 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
571 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
573 #define PLLE_MISC 0x0ec
574 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
575 #define PLLE_MISC_PLL_READY (1 << 15)
576 #define PLLE_MISC_LOCK (1 << 11)
577 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
578 #define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
580 static int tegra_plle_train(void)
582 unsigned int timeout = 2000;
585 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
586 value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
587 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
589 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
590 value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
591 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
593 value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
594 value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
595 writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
598 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
599 if (value & PLLE_MISC_PLL_READY)
606 error("timeout waiting for PLLE to become ready");
613 int tegra_plle_enable(void)
615 unsigned int timeout = 1000;
619 /* disable PLLE clock */
620 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
621 value &= ~PLLE_BASE_ENABLE_CML;
622 value &= ~PLLE_BASE_ENABLE;
623 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
625 /* clear lock enable and setup field */
626 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
627 value &= ~PLLE_MISC_LOCK_ENABLE;
628 value &= ~PLLE_MISC_SETUP_BASE(0xffff);
629 value &= ~PLLE_MISC_SETUP_EXT(0x3);
630 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
632 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
633 if ((value & PLLE_MISC_PLL_READY) == 0) {
634 err = tegra_plle_train();
636 error("failed to train PLLE: %d", err);
641 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
642 value |= PLLE_MISC_SETUP_BASE(0x7);
643 value |= PLLE_MISC_LOCK_ENABLE;
644 value |= PLLE_MISC_SETUP_EXT(0);
645 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
647 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
648 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
649 PLLE_SS_CNTL_BYPASS_SS;
650 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
652 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
653 value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
654 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
657 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
658 if (value & PLLE_MISC_LOCK)
665 error("timeout waiting for PLLE to lock");
671 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
672 value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
673 value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
675 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
676 value |= PLLE_SS_CNTL_SSCINC(0x01);
678 value &= ~PLLE_SS_CNTL_SSCBYP;
679 value &= ~PLLE_SS_CNTL_INTERP_RESET;
680 value &= ~PLLE_SS_CNTL_BYPASS_SS;
682 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
683 value |= PLLE_SS_CNTL_SSCMAX(0x24);
684 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);