2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <asm/arch/tegra.h>
10 #include <asm/arch-tegra/pmc.h>
13 static void enable_cpu_power_rail(void)
15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
18 reg = readl(&pmc->pmc_cntrl);
20 writel(reg, &pmc->pmc_cntrl);
23 * The TI PMU65861C needs a 3.75ms delay between enabling
24 * the power rail and enabling the CPU clock. This delay
25 * between SM1EN and SM1 is for switching time + the ramp
26 * up of the voltage to the CPU (VDD_CPU from PMU).
31 void start_cpu(u32 reset_vector)
34 enable_cpu_power_rail();
36 /* Hold the CPUs in reset */
39 /* Disable the CPU clock */
42 /* Enable CoreSight */
43 clock_enable_coresight(1);
46 * Set the entry point for CPU execution from reset,
47 * if it's a non-zero value.
50 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
52 /* Enable the CPU clock */
55 /* If the CPU doesn't already have power, power it up */
58 /* Take the CPU out of reset */