1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2011 The Chromium OS Authors.
6 /* Tegra20 pin multiplexing functions */
10 #include <asm/arch/pinmux.h>
13 * This defines the order of the pin mux control bits in the registers. For
14 * some reason there is no correspendence between the tristate, pin mux and
15 * pullup/pulldown registers.
18 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
37 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
56 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
75 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
94 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
113 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
132 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
155 * And this defines the order of the pullup/pulldown controls which are again
156 * in a different order
159 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
178 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
196 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
215 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
234 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
256 /* Convenient macro for defining pin group properties */
257 #define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
269 /* A normal pin group where the mux name and pull-up name match */
270 #define PIN(pingrp, f0, f1, f2, f3) \
271 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
273 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
274 #define PINP(pingrp, f0, f1, f2, f3, pupd) \
275 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
277 /* A pin group number which is not used */
278 #define PIN_RESERVED \
279 PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
281 #define DRVGRP(drvgrp) \
282 PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
284 static const struct pmux_pingrp_desc tegra20_pingroups[] = {
285 PIN(ATA, IDE, NAND, GMI, RSVD4),
286 PIN(ATB, IDE, NAND, GMI, SDIO4),
287 PIN(ATC, IDE, NAND, GMI, SDIO4),
288 PIN(ATD, IDE, NAND, GMI, SDIO4),
289 PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
290 PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
291 PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
292 PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
294 PIN(DAP2, DAP2, TWC, RSVD3, GMI),
295 PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
296 PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
297 PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
298 PIN(DTB, RSVD1, RSVD2, VI, SPI1),
299 PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
300 PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
301 PIN(DTE, RSVD1, RSVD2, VI, SPI1),
303 PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
304 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
305 PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
306 PIN(IRTX, UARTA, UARTB, GMI, SPI4),
307 PIN(IRRX, UARTA, UARTB, GMI, SPI4),
308 PIN(KBCB, KBC, NAND, SDIO2, MIO),
309 PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
310 PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
312 PIN(PTA, I2C2, HDMI, GMI, RSVD4),
313 PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
314 PIN(KBCE, KBC, NAND, OWR, RSVD4),
315 PIN(KBCF, KBC, NAND, TRACE, MIO),
316 PIN(GMA, UARTE, SPI3, GMI, SDIO4),
317 PIN(GMC, UARTD, SPI4, GMI, SFLASH),
318 PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
319 PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
321 PIN(GME, RSVD1, DAP5, GMI, SDIO4),
322 PIN(SDC, PWM, TWC, SDIO3, SPI3),
323 PIN(SDD, UARTA, PWM, SDIO3, SPI3),
325 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
326 PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
327 PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
328 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
330 PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
331 PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
332 PIN(SPIA, SPI1, SPI2, SPI3, GMI),
333 PIN(SPIB, SPI1, SPI2, SPI3, GMI),
334 PIN(SPIC, SPI1, SPI2, SPI3, GMI),
335 PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
336 PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
337 PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
339 PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
340 PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
341 PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
342 PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
343 PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
344 PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
345 PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
346 PIN(UCB, UARTC, PWM, GMI, RSVD4),
349 PIN(ATE, IDE, NAND, GMI, RSVD4),
350 PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
353 PIN(GMB, IDE, NAND, GMI, GMI_INT),
354 PIN(GMD, RSVD1, NAND, GMI, SFLASH),
355 PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
358 PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
359 PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
360 PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
361 PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
362 PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
363 PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
364 PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
365 PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
367 PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
368 PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
369 PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
370 PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
371 PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
372 PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
373 PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
374 PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
376 PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
377 PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
378 PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
379 PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
380 PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
381 PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
382 PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
383 PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
385 PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
386 PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
387 PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
388 PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
389 PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
390 PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
391 PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
392 PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
395 PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
396 PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
397 PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
398 PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
399 PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
400 PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
401 PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
402 PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
404 PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
406 PIN(KBCD, KBC, NAND, SDIO2, MIO),
407 PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
408 PIN(DTF, I2C3, RSVD2, VI, RSVD4),
409 PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
410 PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
411 PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
413 /* these pin groups only have pullup and pull down control */
424 const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;