2 * (C) Copyright 2010 - 2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/emc.h>
13 #include <asm/arch/gp_padctrl.h>
14 #include <asm/arch/pinmux.h>
15 #include <asm/arch/sdram_param.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/apb_misc.h>
19 #include <asm/arch-tegra/clk_rst.h>
20 #include <asm/arch-tegra/pmc.h>
21 #include <asm/arch-tegra/fuse.h>
22 #include <asm/arch-tegra/warmboot.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #ifndef CONFIG_TEGRA_CLOCK_SCALING
27 #error "You must enable CONFIG_TEGRA_CLOCK_SCALING to use CONFIG_TEGRA_LP0"
31 * This is the place in SRAM where the SDRAM parameters are stored. There
32 * are 4 blocks, one for each RAM code
34 #define SDRAM_PARAMS_BASE (NV_PA_BASE_SRAM + 0x188)
36 /* TODO: If we later add support for the Misc GP controller, refactor this */
74 * TODO: This register is not documented in the TRM yet. We could move this
75 * into the EMC and give it a proper interface, but not while it is
78 union fbio_spare_reg {
86 /* We pack the resume information into these unions for later */
90 u32 pllm_base_divn:10;
92 u32 pllm_misc_lfcon:4;
93 u32 pllm_misc_cpcon:4;
94 u32 gp_xm2cfga_padctrl_preemp:1;
95 u32 gp_xm2cfgd_padctrl_schmt:1;
104 u32 emc_clock_divider:8;
105 u32 pllm_stable_time:8;
106 u32 pllx_stable_time:8;
107 u32 emc_fbio_spare_cfg_wb0:8;
112 union scratch24_reg {
114 u32 emc_auto_cal_wait:8;
115 u32 emc_pin_program_wait:8;
122 int warmboot_save_sdram_params(void)
125 struct sdram_params sdram;
126 struct apb_misc_pp_ctlr *apb_misc =
127 (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
128 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
129 struct apb_misc_gp_ctlr *gp =
130 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
131 struct emc_ctlr *emc = emc_get_controller(gd->fdt_blob);
132 union scratch2_reg scratch2;
133 union scratch4_reg scratch4;
134 union scratch24_reg scratch24;
135 union xm2cfga_reg xm2cfga;
136 union xm2cfgd_reg xm2cfgd;
137 union fbio_spare_reg fbio_spare;
139 /* get ram code that is used as index to array sdram_params in BCT */
140 ram_code = (readl(&apb_misc->strapping_opt_a) >>
141 STRAP_OPT_A_RAM_CODE_SHIFT) & 3;
143 (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code),
146 xm2cfga.word = readl(&gp->xm2cfga);
147 xm2cfgd.word = readl(&gp->xm2cfgd);
150 scratch2.osc_ctrl_xobp = clock_get_osc_bypass();
152 /* Get the memory PLL settings */
154 u32 divm, divn, divp, cpcon, lfcon;
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp,
159 scratch2.pllm_base_divm = divm;
160 scratch2.pllm_base_divn = divn;
161 scratch2.pllm_base_divp = divp;
162 scratch2.pllm_misc_cpcon = cpcon;
163 scratch2.pllm_misc_lfcon = lfcon;
166 scratch2.gp_xm2cfga_padctrl_preemp = xm2cfga.preemp_en;
167 scratch2.gp_xm2cfgd_padctrl_schmt = xm2cfgd.schmt_en;
168 scratch2.memory_type = sdram.memory_type;
169 writel(scratch2.word, &pmc->pmc_scratch2);
171 /* collect data from various sources for pmc_scratch4 */
172 fbio_spare.word = readl(&emc->fbio_spare);
174 scratch4.emc_fbio_spare_cfg_wb0 = fbio_spare.cfg_wb0;
175 scratch4.emc_clock_divider = sdram.emc_clock_divider;
176 scratch4.pllm_stable_time = -1;
177 scratch4.pllx_stable_time = -1;
178 writel(scratch4.word, &pmc->pmc_scratch4);
180 /* collect various data from sdram for pmc_scratch24 */
182 scratch24.emc_pin_program_wait = sdram.emc_pin_program_wait;
183 scratch24.emc_auto_cal_wait = sdram.emc_auto_cal_wait;
184 scratch24.warmboot_wait = sdram.warm_boot_wait;
185 writel(scratch24.word, &pmc->pmc_scratch24);
190 static u32 get_major_version(void)
193 struct apb_misc_gp_ctlr *gp =
194 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
196 major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >>
197 HIDREV_MAJORPREV_SHIFT;
201 static int is_production_mode_fuse_set(struct fuse_regs *fuse)
203 return readl(&fuse->production_mode);
206 static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse)
208 return readl(&fuse->security_mode);
211 static int is_failure_analysis_mode(struct fuse_regs *fuse)
213 return readl(&fuse->fa);
216 static int ap20_is_odm_production_mode(void)
218 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
220 if (!is_failure_analysis_mode(fuse) &&
221 is_odm_production_mode_fuse_set(fuse))
227 static int ap20_is_production_mode(void)
229 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
231 if (get_major_version() == 0)
234 if (!is_failure_analysis_mode(fuse) &&
235 is_production_mode_fuse_set(fuse) &&
236 !is_odm_production_mode_fuse_set(fuse))
242 static enum fuse_operating_mode fuse_get_operation_mode(void)
245 struct apb_misc_gp_ctlr *gp =
246 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
248 chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >>
250 if (chip_id == CHIPID_TEGRA20) {
251 if (ap20_is_odm_production_mode()) {
252 printf("!! odm_production_mode is not supported !!\n");
253 return MODE_UNDEFINED;
255 if (ap20_is_production_mode())
256 return MODE_PRODUCTION;
258 return MODE_UNDEFINED;
260 return MODE_UNDEFINED;
263 static void determine_crypto_options(int *is_encrypted, int *is_signed,
266 switch (fuse_get_operation_mode()) {
267 case MODE_PRODUCTION:
281 static int sign_wb_code(u32 start, u32 length, int use_zero_key)
284 u8 *source; /* Pointer to source */
287 /* Calculate AES block parameters. */
288 source = (u8 *)(start + offsetof(struct wb_header, random_aes_block));
289 length -= offsetof(struct wb_header, random_aes_block);
290 hash = (u8 *)(start + offsetof(struct wb_header, hash));
291 err = sign_data_block(source, length, hash);
296 int warmboot_prepare_code(u32 seg_address, u32 seg_length)
299 u32 length; /* length of the signed/encrypt code */
300 struct wb_header *dst_header; /* Pointer to dest WB header */
301 int is_encrypted; /* Segment is encrypted */
302 int is_signed; /* Segment is signed */
303 int use_zero_key; /* Use key of all zeros */
305 /* Determine crypto options. */
306 determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key);
308 /* Get the actual code limits. */
309 length = roundup(((u32)wb_end - (u32)wb_start), 16);
312 * The region specified by seg_address must be in SDRAM and must be
315 if (seg_length == 0 || seg_address < NV_PA_SDRAM_BASE ||
316 seg_address + seg_length >= NV_PA_SDRAM_BASE + gd->ram_size) {
321 /* Things must be 16-byte aligned. */
322 if ((seg_length & 0xF) || (seg_address & 0xF)) {
327 /* Will the code fit? (destination includes wb_header + wb code) */
328 if (seg_length < (length + sizeof(struct wb_header))) {
333 dst_header = (struct wb_header *)seg_address;
334 memset((char *)dst_header, 0, sizeof(struct wb_header));
336 /* Populate the random_aes_block as requested. */
338 u32 *aes_block = (u32 *)&(dst_header->random_aes_block);
339 u32 *end = (u32 *)(((u32)aes_block) +
340 sizeof(dst_header->random_aes_block));
344 } while (aes_block < end);
347 /* Populate the header. */
348 dst_header->length_insecure = length + sizeof(struct wb_header);
349 dst_header->length_secure = length + sizeof(struct wb_header);
350 dst_header->destination = NV_WB_RUN_ADDRESS;
351 dst_header->entry_point = NV_WB_RUN_ADDRESS;
352 dst_header->code_length = length;
355 printf("!!!! Encryption is not supported !!!!\n");
356 dst_header->length_insecure = 0;
360 /* copy the wb code directly following dst_header. */
361 memcpy((char *)(dst_header+1), (char *)wb_start, length);
364 err = sign_wb_code(seg_address, dst_header->length_insecure,
369 printf("Warning: warmboot code copy failed (error=%d)\n", err);