2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
12 #include "../xusb-padctl-common.h"
14 #include <asm/arch/clock.h>
16 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
18 enum tegra210_function {
22 TEGRA210_FUNC_PCIE_X1,
23 TEGRA210_FUNC_PCIE_X4,
29 static const char *const tegra210_functions[] = {
40 static const unsigned int tegra210_otg_functions[] = {
47 static const unsigned int tegra210_usb_functions[] = {
52 static const unsigned int tegra210_pci_functions[] = {
53 TEGRA210_FUNC_PCIE_X1,
56 TEGRA210_FUNC_PCIE_X4,
59 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \
66 .num_funcs = ARRAY_SIZE(tegra210_##_funcs##_functions), \
67 .funcs = tegra210_##_funcs##_functions, \
70 static const struct tegra_xusb_padctl_lane tegra210_lanes[] = {
71 TEGRA210_LANE("otg-0", 0x004, 0, 0x3, 0, otg),
72 TEGRA210_LANE("otg-1", 0x004, 2, 0x3, 0, otg),
73 TEGRA210_LANE("otg-2", 0x004, 4, 0x3, 0, otg),
74 TEGRA210_LANE("otg-3", 0x004, 6, 0x3, 0, otg),
75 TEGRA210_LANE("usb2-bias", 0x004, 18, 0x3, 0, otg),
76 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, 0, usb),
77 TEGRA210_LANE("hsic-1", 0x004, 15, 0x1, 0, usb),
78 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, 1, pci),
79 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, 2, pci),
80 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, 3, pci),
81 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, 4, pci),
82 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, 5, pci),
83 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, 6, pci),
84 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, 7, pci),
85 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, 8, pci),
88 #define XUSB_PADCTL_ELPG_PROGRAM 0x024
89 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
90 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
91 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 29)
93 static int tegra_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
97 if (padctl->enable++ > 0)
100 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
101 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
102 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
106 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
107 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
108 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
112 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
113 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
114 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
119 static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
123 if (padctl->enable == 0) {
124 error("unbalanced enable/disable");
128 if (--padctl->enable > 0)
131 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
132 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN;
133 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
137 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
138 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY;
139 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
143 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
144 value |= XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN;
145 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
150 static int phy_prepare(struct tegra_xusb_phy *phy)
154 err = tegra_xusb_padctl_enable(phy->padctl);
158 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 0);
163 static int phy_unprepare(struct tegra_xusb_phy *phy)
165 reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
167 return tegra_xusb_padctl_disable(phy->padctl);
170 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
171 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
172 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
173 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16)
174 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS (1 << 15)
175 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4)
176 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3)
177 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK (0x3 << 1)
178 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(x) (((x) & 0x3) << 1)
179 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ (1 << 0)
181 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
182 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK (0xffffff << 4)
183 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(x) (((x) & 0xffffff) << 4)
184 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD (1 << 2)
185 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE (1 << 1)
186 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN (1 << 0)
188 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
189 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN (1 << 15)
190 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK (0x3 << 12)
191 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(x) (((x) & 0x3) << 12)
192 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN (1 << 8)
193 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK (0xf << 4)
195 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
196 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK (0xff << 16)
197 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(x) (((x) & 0xff) << 16)
199 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
200 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE (1 << 31)
201 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD (1 << 15)
202 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN (1 << 13)
203 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN (1 << 12)
205 #define CLK_RST_XUSBIO_PLL_CFG0 0x51c
206 #define CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE (1 << 24)
207 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ (1 << 13)
208 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET (1 << 6)
209 #define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2)
210 #define CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL (1 << 0)
212 static int pcie_phy_enable(struct tegra_xusb_phy *phy)
214 struct tegra_xusb_padctl *padctl = phy->padctl;
218 debug("> %s(phy=%p)\n", __func__, phy);
220 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
221 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL_MASK;
222 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_CTRL(0x136);
223 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
225 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
226 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL_MASK;
227 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL5_DCO_CTRL(0x2a);
228 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
230 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
231 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
232 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
234 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
235 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
236 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
238 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
239 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
240 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
242 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
243 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL_MASK;
244 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLK_SEL_MASK;
245 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_SEL(2);
246 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_TXCLKREF_EN;
247 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
249 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
250 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK;
251 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK;
252 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(25);
253 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
255 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
256 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
257 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
259 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
260 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
261 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
265 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
266 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL4_REFCLKBUF_EN;
267 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
269 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
270 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
271 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
273 debug(" waiting for calibration\n");
275 start = get_timer(0);
277 while (get_timer(start) < 250) {
278 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
279 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
282 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
288 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
289 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_EN;
290 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
292 debug(" waiting for calibration to stop\n");
294 start = get_timer(0);
296 while (get_timer(start) < 250) {
297 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
298 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
301 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
307 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
308 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
309 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
311 debug(" waiting for PLL to lock...\n");
312 start = get_timer(0);
314 while (get_timer(start) < 250) {
315 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
316 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
319 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
325 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
326 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
327 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
328 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
330 debug(" waiting for register calibration...\n");
331 start = get_timer(0);
333 while (get_timer(start) < 250) {
334 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
335 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
338 if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
344 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
345 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_EN;
346 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
348 debug(" waiting for register calibration to stop...\n");
349 start = get_timer(0);
351 while (get_timer(start) < 250) {
352 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
353 if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
356 if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
362 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
363 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
364 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
366 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
367 value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
368 value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
369 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
370 value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
371 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
373 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
374 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
375 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
377 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
378 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
379 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
381 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
382 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
383 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
387 value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
388 value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
389 writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
391 debug("< %s()\n", __func__);
395 static int pcie_phy_disable(struct tegra_xusb_phy *phy)
400 static const struct tegra_xusb_phy_ops pcie_phy_ops = {
401 .prepare = phy_prepare,
402 .enable = pcie_phy_enable,
403 .disable = pcie_phy_disable,
404 .unprepare = phy_unprepare,
407 static struct tegra_xusb_phy tegra210_phys[] = {
409 .type = TEGRA_XUSB_PADCTL_PCIE,
410 .ops = &pcie_phy_ops,
415 static const struct tegra_xusb_padctl_soc tegra210_socdata = {
416 .lanes = tegra210_lanes,
417 .num_lanes = ARRAY_SIZE(tegra210_lanes),
418 .functions = tegra210_functions,
419 .num_functions = ARRAY_SIZE(tegra210_functions),
420 .phys = tegra210_phys,
421 .num_phys = ARRAY_SIZE(tegra210_phys),
424 void tegra_xusb_padctl_init(const void *fdt)
428 debug("> %s(fdt=%p)\n", __func__, fdt);
430 count = fdtdec_find_aliases_for_id(fdt, "padctl",
431 COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
432 nodes, ARRAY_SIZE(nodes));
433 if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata))
436 debug("< %s()\n", __func__);