2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #define pr_fmt(fmt) "tegra-xusb-padctl: " fmt
12 #include "xusb-padctl-common.h"
14 #include <asm/arch/clock.h>
16 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy)
18 if (phy && phy->ops && phy->ops->prepare)
19 return phy->ops->prepare(phy);
21 return phy ? -ENOSYS : -EINVAL;
24 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy)
26 if (phy && phy->ops && phy->ops->enable)
27 return phy->ops->enable(phy);
29 return phy ? -ENOSYS : -EINVAL;
32 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy)
34 if (phy && phy->ops && phy->ops->disable)
35 return phy->ops->disable(phy);
37 return phy ? -ENOSYS : -EINVAL;
40 int tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
42 if (phy && phy->ops && phy->ops->unprepare)
43 return phy->ops->unprepare(phy);
45 return phy ? -ENOSYS : -EINVAL;
48 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type)
50 struct tegra_xusb_phy *phy;
53 for (i = 0; i < padctl.socdata->num_phys; i++) {
54 phy = &padctl.socdata->phys[i];
55 if (phy->type != type)
63 static const struct tegra_xusb_padctl_lane *
64 tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name)
68 for (i = 0; i < padctl->socdata->num_lanes; i++)
69 if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
70 return &padctl->socdata->lanes[i];
76 tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
77 struct tegra_xusb_padctl_group *group,
83 group->name = ofnode_get_name(node);
85 len = ofnode_read_string_count(node, "nvidia,lanes");
87 pr_err("failed to parse \"nvidia,lanes\" property");
91 group->num_pins = len;
93 for (i = 0; i < group->num_pins; i++) {
94 ret = ofnode_read_string_index(node, "nvidia,lanes", i,
97 pr_err("failed to read string from \"nvidia,lanes\" property");
102 group->num_pins = len;
104 ret = ofnode_read_string_index(node, "nvidia,function", 0,
107 pr_err("failed to parse \"nvidia,func\" property");
111 group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1);
116 static int tegra_xusb_padctl_find_function(struct tegra_xusb_padctl *padctl,
121 for (i = 0; i < padctl->socdata->num_functions; i++)
122 if (strcmp(name, padctl->socdata->functions[i]) == 0)
129 tegra_xusb_padctl_lane_find_function(struct tegra_xusb_padctl *padctl,
130 const struct tegra_xusb_padctl_lane *lane,
136 func = tegra_xusb_padctl_find_function(padctl, name);
140 for (i = 0; i < lane->num_funcs; i++)
141 if (lane->funcs[i] == func)
148 tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
149 const struct tegra_xusb_padctl_group *group)
153 for (i = 0; i < group->num_pins; i++) {
154 const struct tegra_xusb_padctl_lane *lane;
158 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
160 pr_err("no lane for pin %s", group->pins[i]);
164 func = tegra_xusb_padctl_lane_find_function(padctl, lane,
167 pr_err("function %s invalid for lane %s: %d",
168 group->func, lane->name, func);
172 value = padctl_readl(padctl, lane->offset);
174 /* set pin function */
175 value &= ~(lane->mask << lane->shift);
176 value |= func << lane->shift;
179 * Set IDDQ if supported on the lane and specified in the
182 if (lane->iddq > 0 && group->iddq >= 0) {
183 if (group->iddq != 0)
184 value &= ~(1 << lane->iddq);
186 value |= 1 << lane->iddq;
189 padctl_writel(padctl, value, lane->offset);
196 tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
197 struct tegra_xusb_padctl_config *config)
201 for (i = 0; i < config->num_groups; i++) {
202 const struct tegra_xusb_padctl_group *group;
205 group = &config->groups[i];
207 err = tegra_xusb_padctl_group_apply(padctl, group);
209 pr_err("failed to apply group %s: %d",
219 tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
220 struct tegra_xusb_padctl_config *config,
225 config->name = ofnode_get_name(node);
227 ofnode_for_each_subnode(subnode, node) {
228 struct tegra_xusb_padctl_group *group;
231 group = &config->groups[config->num_groups];
233 err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
235 pr_err("failed to parse group %s", group->name);
239 config->num_groups++;
245 static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
251 err = ofnode_read_resource(node, 0, &padctl->regs);
253 pr_err("registers not found");
257 ofnode_for_each_subnode(subnode, node) {
258 struct tegra_xusb_padctl_config *config = &padctl->config;
260 debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode));
261 err = tegra_xusb_padctl_config_parse_dt(padctl, config,
264 pr_err("failed to parse entry %s: %d",
269 debug("%s: done\n", __func__);
274 struct tegra_xusb_padctl padctl;
276 int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
277 const struct tegra_xusb_padctl_soc *socdata)
282 debug("%s: count=%d\n", __func__, count);
283 for (i = 0; i < count; i++) {
284 debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np);
285 if (!ofnode_is_available(nodes[i]))
288 padctl.socdata = socdata;
290 err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
292 pr_err("failed to parse DT: %d", err);
296 /* deassert XUSB padctl reset */
297 reset_set_enable(PERIPH_ID_XUSB_PADCTL, 0);
299 err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
301 pr_err("failed to apply pinmux: %d", err);
305 /* only a single instance is supported */
308 debug("%s: done\n", __func__);