2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
8 #define _TEGRA_XUSB_PADCTL_COMMON_H_
14 #include <asm/arch-tegra/xusb-padctl.h>
16 struct tegra_xusb_padctl_lane {
24 const unsigned int *funcs;
25 unsigned int num_funcs;
28 struct tegra_xusb_phy_ops {
29 int (*prepare)(struct tegra_xusb_phy *phy);
30 int (*enable)(struct tegra_xusb_phy *phy);
31 int (*disable)(struct tegra_xusb_phy *phy);
32 int (*unprepare)(struct tegra_xusb_phy *phy);
35 struct tegra_xusb_phy {
36 const struct tegra_xusb_phy_ops *ops;
38 struct tegra_xusb_padctl *padctl;
41 struct tegra_xusb_padctl_pin {
42 const struct tegra_xusb_padctl_lane *lane;
51 struct tegra_xusb_padctl_group {
54 const char *pins[MAX_PINS];
55 unsigned int num_pins;
61 struct tegra_xusb_padctl_config {
64 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
65 unsigned int num_groups;
68 struct tegra_xusb_padctl {
69 struct fdt_resource regs;
73 struct tegra_xusb_phy phys[2];
75 const struct tegra_xusb_padctl_lane *lanes;
76 unsigned int num_lanes;
78 const char *const *functions;
79 unsigned int num_functions;
81 struct tegra_xusb_padctl_config config;
84 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
87 return readl(padctl->regs.start + offset);
90 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
91 u32 value, unsigned long offset)
93 writel(value, padctl->regs.start + offset);
96 extern struct tegra_xusb_padctl *padctl;
98 int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
99 const void *fdt, int node);
100 int tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
101 struct tegra_xusb_padctl_config *config);