2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
8 #define _TEGRA_XUSB_PADCTL_COMMON_H_
12 #include <dm/ofnode.h>
15 #include <asm/arch-tegra/xusb-padctl.h>
16 #include <linux/ioport.h>
18 struct tegra_xusb_padctl_lane {
26 const unsigned int *funcs;
27 unsigned int num_funcs;
30 struct tegra_xusb_phy_ops {
31 int (*prepare)(struct tegra_xusb_phy *phy);
32 int (*enable)(struct tegra_xusb_phy *phy);
33 int (*disable)(struct tegra_xusb_phy *phy);
34 int (*unprepare)(struct tegra_xusb_phy *phy);
37 struct tegra_xusb_phy {
39 const struct tegra_xusb_phy_ops *ops;
40 struct tegra_xusb_padctl *padctl;
43 struct tegra_xusb_padctl_pin {
44 const struct tegra_xusb_padctl_lane *lane;
53 struct tegra_xusb_padctl_group {
56 const char *pins[MAX_PINS];
57 unsigned int num_pins;
63 struct tegra_xusb_padctl_soc {
64 const struct tegra_xusb_padctl_lane *lanes;
65 unsigned int num_lanes;
66 const char *const *functions;
67 unsigned int num_functions;
68 struct tegra_xusb_phy *phys;
69 unsigned int num_phys;
72 struct tegra_xusb_padctl_config {
75 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
76 unsigned int num_groups;
79 struct tegra_xusb_padctl {
80 const struct tegra_xusb_padctl_soc *socdata;
81 struct tegra_xusb_padctl_config config;
86 extern struct tegra_xusb_padctl padctl;
88 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
91 return readl(padctl->regs.start + offset);
94 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
95 u32 value, unsigned long offset)
97 writel(value, padctl->regs.start + offset);
100 int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
101 const struct tegra_xusb_padctl_soc *socdata);