2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
8 #define _TEGRA_XUSB_PADCTL_COMMON_H_
14 #include <asm/arch-tegra/xusb-padctl.h>
16 struct tegra_xusb_padctl_lane {
24 const unsigned int *funcs;
25 unsigned int num_funcs;
28 struct tegra_xusb_phy_ops {
29 int (*prepare)(struct tegra_xusb_phy *phy);
30 int (*enable)(struct tegra_xusb_phy *phy);
31 int (*disable)(struct tegra_xusb_phy *phy);
32 int (*unprepare)(struct tegra_xusb_phy *phy);
35 struct tegra_xusb_phy {
37 const struct tegra_xusb_phy_ops *ops;
38 struct tegra_xusb_padctl *padctl;
41 struct tegra_xusb_padctl_pin {
42 const struct tegra_xusb_padctl_lane *lane;
51 struct tegra_xusb_padctl_group {
54 const char *pins[MAX_PINS];
55 unsigned int num_pins;
61 struct tegra_xusb_padctl_soc {
62 const struct tegra_xusb_padctl_lane *lanes;
63 unsigned int num_lanes;
64 const char *const *functions;
65 unsigned int num_functions;
66 struct tegra_xusb_phy *phys;
67 unsigned int num_phys;
70 struct tegra_xusb_padctl_config {
73 struct tegra_xusb_padctl_group groups[MAX_GROUPS];
74 unsigned int num_groups;
77 struct tegra_xusb_padctl {
78 const struct tegra_xusb_padctl_soc *socdata;
79 struct tegra_xusb_padctl_config config;
80 struct fdt_resource regs;
84 extern struct tegra_xusb_padctl padctl;
86 static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
89 return readl(padctl->regs.start + offset);
92 static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
93 u32 value, unsigned long offset)
95 writel(value, padctl->regs.start + offset);
98 int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
99 const struct tegra_xusb_padctl_soc *socdata);