2 * UniPhier System Cache (L2 Cache) registers
4 * Copyright (C) 2011-2014 Panasonic Corporation
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef ARCH_SSC_REGS_H
10 #define ARCH_SSC_REGS_H
12 #define SSCC 0x500c0000
13 #define SSCC_BST (0x1 << 20)
14 #define SSCC_ACT (0x1 << 19)
15 #define SSCC_WTG (0x1 << 18)
16 #define SSCC_PRD (0x1 << 17)
17 #define SSCC_WBWA (0x1 << 16)
18 #define SSCC_EX (0x1 << 13)
19 #define SSCC_ON (0x1 << 0)
21 #define SSCLPDAWCR 0x500c0030
23 #define SSCOPE 0x506c0244
24 #define SSCOPE_CM_SYNC 0x00000008
26 #define SSCOQM 0x506c0248
27 #define SSCOQM_TID_MASK (0x3 << 21)
28 #define SSCOQM_TID_BY_WAY (0x2 << 21)
29 #define SSCOQM_TID_BY_INST_WAY (0x1 << 21)
30 #define SSCOQM_TID_BY_DATA_WAY (0x0 << 21)
31 #define SSCOQM_S_MASK (0x3 << 17)
32 #define SSCOQM_S_WAY (0x2 << 17)
33 #define SSCOQM_S_ALL (0x1 << 17)
34 #define SSCOQM_S_ADDRESS (0x0 << 17)
35 #define SSCOQM_CE (0x1 << 15)
36 #define SSCOQM_CW (0x1 << 14)
37 #define SSCOQM_CM_MASK (0x7)
38 #define SSCOQM_CM_DIRT_TOUCH (0x7)
39 #define SSCOQM_CM_ZERO_TOUCH (0x6)
40 #define SSCOQM_CM_NORM_TOUCH (0x5)
41 #define SSCOQM_CM_PREF_FETCH (0x4)
42 #define SSCOQM_CM_SSC_FETCH (0x3)
43 #define SSCOQM_CM_WB_INV (0x2)
44 #define SSCOQM_CM_WB (0x1)
45 #define SSCOQM_CM_INV (0x0)
47 #define SSCOQAD 0x506c024c
48 #define SSCOQSZ 0x506c0250
49 #define SSCOQWN 0x506c0258
51 #define SSCOPPQSEF 0x506c025c
52 #define SSCOPPQSEF_FE (0x1 << 1)
53 #define SSCOPPQSEF_OE (0x1 << 0)
55 #define SSCOLPQS 0x506c0260
56 #define SSCOLPQS_EF (0x1 << 2)
57 #define SSCOLPQS_EST (0x1 << 1)
58 #define SSCOLPQS_QST (0x1 << 0)
60 #define SSCOQCE0 0x506c0270
62 #define SSC_LINE_SIZE 128
63 #define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
65 #endif /* ARCH_SSC_REGS_H */