2 * UniPhier System Cache (L2 Cache) registers
4 * Copyright (C) 2011-2014 Panasonic Corporation
5 * Copyright (C) 2016 Socionext Inc.
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef ARCH_SSC_REGS_H
11 #define ARCH_SSC_REGS_H
13 /* control registers */
14 #define UNIPHIER_SSCC 0x500c0000 /* Control Register */
15 #define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
16 #define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
17 #define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
18 #define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
19 #define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
20 #define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
21 #define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
23 /* revision registers */
24 #define UNIPHIER_SSCID 0x503c0100 /* ID Register */
26 /* operation registers */
27 #define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
28 #define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
29 #define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
30 #define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
31 #define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
32 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
33 #define UNIPHIER_SSCOQM 0x506c0248
34 #define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
35 #define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
36 #define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
37 #define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
38 #define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
39 #define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
40 #define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
41 #define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
42 #define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */
43 #define UNIPHIER_SSCOQM_CW (0x1 << 14)
44 #define UNIPHIER_SSCOQM_CM_MASK (0x7)
45 #define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
46 #define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
47 #define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
48 #define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
49 #define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
50 #define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
51 #define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
52 #define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
53 #define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
54 #define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
55 #define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
56 #define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
57 #define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
58 #define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1)
59 #define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0)
60 #define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
61 #define UNIPHIER_SSCOLPQS_EF (0x1 << 2)
62 #define UNIPHIER_SSCOLPQS_EST (0x1 << 1)
63 #define UNIPHIER_SSCOLPQS_QST (0x1 << 0)
65 #define UNIPHIER_SSC_LINE_SIZE 128
66 #define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
68 #endif /* ARCH_SSC_REGS_H */