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   1 /*
   2  * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect
   3  *
   4  * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <mapmem.h>
  11 #include <linux/bitops.h>
  12 #include <linux/io.h>
  13 #include <linux/sizes.h>
  14
  15 #define CCI500_BASE                     0x5FD00000
  16 #define CCI500_SLAVE_OFFSET             0x1000
  17
  18 #define CCI500_SNOOP_CTRL
  19 #define   CCI500_SNOOP_CTRL_EN_DVM      BIT(1)
  20 #define   CCI500_SNOOP_CTRL_EN_SNOOP    BIT(0)
  21
  22 void cci500_init(unsigned int nr_slaves)
  23 {
  24         unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET;
  25         int i;
  26
  27         for (i = 0; i < nr_slaves; i++) {
  28                 void __iomem *base;
  29                 u32 tmp;
  30
  31                 base = map_sysmem(slave_base, SZ_4K);
  32
  33                 tmp = readl(base);
  34                 tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP;
  35                 writel(tmp, base);
  36
  37                 unmap_sysmem(base);
  38
  39                 slave_base += CCI500_SLAVE_OFFSET;
  40         }
  41 }