git.sur5r.net Git - u-boot/blob - arch/arm/mach-uniphier/board_init.c

   1 /*
   2  * Copyright (C) 2012-2015 Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <libfdt.h>
  11 #include <linux/io.h>
  12
  13 #include "init.h"
  14 #include "micro-support-card.h"
  15 #include "sg-regs.h"
  16 #include "soc-info.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static void uniphier_setup_xirq(void)
  21 {
  22         const void *fdt = gd->fdt_blob;
  23         int soc_node, aidet_node;
  24         const u32 *val;
  25         unsigned long aidet_base;
  26         u32 tmp;
  27
  28         soc_node = fdt_path_offset(fdt, "/soc");
  29         if (soc_node < 0)
  30                 return;
  31
  32         aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
  33         if (aidet_node < 0)
  34                 return;
  35
  36         val = fdt_getprop(fdt, aidet_node, "reg", NULL);
  37         if (!val)
  38                 return;
  39
  40         aidet_base = fdt32_to_cpu(*val);
  41
  42         tmp = readl(aidet_base + 8);    /* AIDET DETCONFR2 */
  43         tmp |= 0x00ff0000;              /* Set XIRQ0-7 low active */
  44         writel(tmp, aidet_base + 8);
  45
  46         tmp = readl(0x55000090);        /* IRQCTL */
  47         tmp |= 0x000000ff;
  48         writel(tmp, 0x55000090);
  49 }
  50
  51 static void uniphier_nand_pin_init(bool cs2)
  52 {
  53 #ifdef CONFIG_NAND_DENALI
  54         if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp"))
  55                 pr_err("failed to init NAND pins\n");
  56 #endif
  57 }
  58
  59 int board_init(void)
  60 {
  61         const struct uniphier_board_data *bd;
  62
  63         led_puts("U0");
  64
  65         bd = uniphier_get_board_param();
  66         if (!bd)
  67                 return -ENODEV;
  68
  69         switch (uniphier_get_soc_type()) {
  70 #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
  71         case SOC_UNIPHIER_SLD3:
  72                 uniphier_nand_pin_init(true);
  73                 led_puts("U1");
  74                 uniphier_sld3_pll_init();
  75                 uniphier_ld4_clk_init();
  76                 break;
  77 #endif
  78 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
  79         case SOC_UNIPHIER_LD4:
  80                 uniphier_nand_pin_init(true);
  81                 led_puts("U1");
  82                 uniphier_ld4_pll_init();
  83                 uniphier_ld4_clk_init();
  84                 break;
  85 #endif
  86 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
  87         case SOC_UNIPHIER_PRO4:
  88                 uniphier_nand_pin_init(false);
  89                 led_puts("U1");
  90                 uniphier_pro4_pll_init();
  91                 uniphier_pro4_clk_init();
  92                 break;
  93 #endif
  94 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
  95         case SOC_UNIPHIER_SLD8:
  96                 uniphier_nand_pin_init(true);
  97                 led_puts("U1");
  98                 uniphier_ld4_pll_init();
  99                 uniphier_ld4_clk_init();
 100                 break;
 101 #endif
 102 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 103         case SOC_UNIPHIER_PRO5:
 104                 uniphier_nand_pin_init(true);
 105                 led_puts("U1");
 106                 uniphier_pro5_clk_init();
 107                 break;
 108 #endif
 109 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
 110         case SOC_UNIPHIER_PXS2:
 111                 uniphier_nand_pin_init(true);
 112                 led_puts("U1");
 113                 uniphier_pxs2_clk_init();
 114                 break;
 115 #endif
 116 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 117         case SOC_UNIPHIER_LD6B:
 118                 uniphier_nand_pin_init(true);
 119                 led_puts("U1");
 120                 uniphier_pxs2_clk_init();
 121                 break;
 122 #endif
 123 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
 124         case SOC_UNIPHIER_LD11:
 125                 uniphier_nand_pin_init(false);
 126                 sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0    -> XIRQ0 */
 127                 sg_set_iectrl(149);
 128                 sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4    -> XIRQ4 */
 129                 sg_set_iectrl(153);
 130                 led_puts("U1");
 131                 uniphier_ld11_pll_init();
 132                 uniphier_ld11_clk_init();
 133                 break;
 134 #endif
 135 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 136         case SOC_UNIPHIER_LD20:
 137                 /* ES1 errata: increase VDD09 supply to suppress VBO noise */
 138                 if (uniphier_get_soc_revision() == 1) {
 139                         writel(0x00000003, 0x6184e004);
 140                         writel(0x00000100, 0x6184e040);
 141                         writel(0x0000b500, 0x6184e024);
 142                         writel(0x00000001, 0x6184e000);
 143                 }
 144                 uniphier_nand_pin_init(false);
 145                 sg_set_pinsel(149, 14, 8, 4);   /* XIRQ0    -> XIRQ0 */
 146                 sg_set_iectrl(149);
 147                 sg_set_pinsel(153, 14, 8, 4);   /* XIRQ4    -> XIRQ4 */
 148                 sg_set_iectrl(153);
 149                 led_puts("U1");
 150                 uniphier_ld20_pll_init(bd);
 151                 uniphier_ld20_clk_init();
 152                 cci500_init(2);
 153                 break;
 154 #endif
 155         default:
 156                 break;
 157         }
 158
 159         uniphier_setup_xirq();
 160
 161         led_puts("U2");
 162
 163         support_card_late_init();
 164
 165         led_puts("U3");
 166
 167 #ifdef CONFIG_ARM64
 168         uniphier_smp_kick_all_cpus();
 169 #endif
 170
 171         led_puts("Uboo");
 172
 173         return 0;
 174 }