2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include "micro-support-card.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 static void uniphier_setup_xirq(void)
22 const void *fdt = gd->fdt_blob;
23 int soc_node, aidet_node;
25 unsigned long aidet_base;
28 soc_node = fdt_path_offset(fdt, "/soc");
32 aidet_node = fdt_subnode_offset_namelen(fdt, soc_node, "aidet", 5);
36 val = fdt_getprop(fdt, aidet_node, "reg", NULL);
40 aidet_base = fdt32_to_cpu(*val);
42 tmp = readl(aidet_base + 8); /* AIDET DETCONFR2 */
43 tmp |= 0x00ff0000; /* Set XIRQ0-7 low active */
44 writel(tmp, aidet_base + 8);
46 tmp = readl(0x55000090); /* IRQCTL */
48 writel(tmp, 0x55000090);
51 #ifdef CONFIG_ARCH_UNIPHIER_LD11
52 static void uniphier_ld11_misc_init(void)
54 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
56 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
61 #ifdef CONFIG_ARCH_UNIPHIER_LD20
62 static void uniphier_ld20_misc_init(void)
64 sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */
66 sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */
69 /* ES1 errata: increase VDD09 supply to suppress VBO noise */
70 if (uniphier_get_soc_revision() == 1) {
71 writel(0x00000003, 0x6184e004);
72 writel(0x00000100, 0x6184e040);
73 writel(0x0000b500, 0x6184e024);
74 writel(0x00000001, 0x6184e000);
79 struct uniphier_initdata {
82 void (*sbc_init)(void);
83 void (*pll_init)(void);
84 void (*clk_init)(void);
85 void (*misc_init)(void);
88 static const struct uniphier_initdata uniphier_initdata[] = {
89 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
91 .soc_id = UNIPHIER_LD4_ID,
93 .sbc_init = uniphier_ld4_sbc_init,
94 .pll_init = uniphier_ld4_pll_init,
95 .clk_init = uniphier_ld4_clk_init,
98 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
100 .soc_id = UNIPHIER_PRO4_ID,
102 .sbc_init = uniphier_sbc_init_savepin,
103 .pll_init = uniphier_pro4_pll_init,
104 .clk_init = uniphier_pro4_clk_init,
107 #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
109 .soc_id = UNIPHIER_SLD8_ID,
111 .sbc_init = uniphier_ld4_sbc_init,
112 .pll_init = uniphier_ld4_pll_init,
113 .clk_init = uniphier_ld4_clk_init,
116 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
118 .soc_id = UNIPHIER_PRO5_ID,
120 .sbc_init = uniphier_sbc_init_savepin,
121 .clk_init = uniphier_pro5_clk_init,
124 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
126 .soc_id = UNIPHIER_PXS2_ID,
128 .sbc_init = uniphier_pxs2_sbc_init,
129 .clk_init = uniphier_pxs2_clk_init,
132 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
134 .soc_id = UNIPHIER_LD6B_ID,
136 .sbc_init = uniphier_pxs2_sbc_init,
137 .clk_init = uniphier_pxs2_clk_init,
140 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
142 .soc_id = UNIPHIER_LD11_ID,
144 .sbc_init = uniphier_ld11_sbc_init,
145 .pll_init = uniphier_ld11_pll_init,
146 .clk_init = uniphier_ld11_clk_init,
147 .misc_init = uniphier_ld11_misc_init,
150 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
152 .soc_id = UNIPHIER_LD20_ID,
154 .sbc_init = uniphier_ld11_sbc_init,
155 .pll_init = uniphier_ld20_pll_init,
156 .clk_init = uniphier_ld20_clk_init,
157 .misc_init = uniphier_ld20_misc_init,
160 #if defined(CONFIG_ARCH_UNIPHIER_PXS3)
162 .soc_id = UNIPHIER_PXS3_ID,
164 .sbc_init = uniphier_pxs2_sbc_init,
165 .pll_init = uniphier_pxs3_pll_init,
166 .clk_init = uniphier_pxs3_clk_init,
170 UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_initdata, uniphier_initdata)
174 const struct uniphier_initdata *initdata;
179 initdata = uniphier_get_initdata();
181 pr_err("unsupported SoC\n");
185 initdata->sbc_init();
191 if (IS_ENABLED(CONFIG_NAND_DENALI)) {
192 ret = uniphier_pin_init(initdata->nand_2cs ?
193 "nand2cs_grp" : "nand_grp");
195 pr_err("failed to init NAND pins\n");
200 if (initdata->pll_init)
201 initdata->pll_init();
205 if (initdata->clk_init)
206 initdata->clk_init();
210 if (initdata->misc_init)
211 initdata->misc_init();
215 uniphier_setup_xirq();
219 support_card_late_init();