2 * Copyright (C) 2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
11 #include <linux/compat.h>
13 #include <asm/processor.h>
15 #include "../soc-info.h"
17 #define MMC_CMD_SWITCH 6
18 #define MMC_CMD_SELECT_CARD 7
19 #define MMC_CMD_SEND_CSD 9
20 #define MMC_CMD_READ_MULTIPLE_BLOCK 18
22 #define EXT_CSD_PART_CONF 179 /* R/W */
24 #define MMC_RSP_PRESENT BIT(0)
25 #define MMC_RSP_136 BIT(1) /* 136 bit response */
26 #define MMC_RSP_CRC BIT(2) /* expect valid crc */
27 #define MMC_RSP_BUSY BIT(3) /* card may send busy */
28 #define MMC_RSP_OPCODE BIT(4) /* response contains opcode */
30 #define MMC_RSP_NONE (0)
31 #define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
32 #define MMC_RSP_R1b (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | \
34 #define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
35 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
36 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
37 #define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
38 #define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
39 #define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
41 #define SDHCI_DMA_ADDRESS 0x00
42 #define SDHCI_BLOCK_SIZE 0x04
43 #define SDHCI_MAKE_BLKSZ(dma, blksz) ((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))
44 #define SDHCI_BLOCK_COUNT 0x06
45 #define SDHCI_ARGUMENT 0x08
46 #define SDHCI_TRANSFER_MODE 0x0C
47 #define SDHCI_TRNS_DMA BIT(0)
48 #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
49 #define SDHCI_TRNS_ACMD12 BIT(2)
50 #define SDHCI_TRNS_READ BIT(4)
51 #define SDHCI_TRNS_MULTI BIT(5)
52 #define SDHCI_COMMAND 0x0E
53 #define SDHCI_CMD_RESP_MASK 0x03
54 #define SDHCI_CMD_CRC 0x08
55 #define SDHCI_CMD_INDEX 0x10
56 #define SDHCI_CMD_DATA 0x20
57 #define SDHCI_CMD_ABORTCMD 0xC0
58 #define SDHCI_CMD_RESP_NONE 0x00
59 #define SDHCI_CMD_RESP_LONG 0x01
60 #define SDHCI_CMD_RESP_SHORT 0x02
61 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
62 #define SDHCI_MAKE_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
63 #define SDHCI_RESPONSE 0x10
64 #define SDHCI_HOST_CONTROL 0x28
65 #define SDHCI_CTRL_DMA_MASK 0x18
66 #define SDHCI_CTRL_SDMA 0x00
67 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
68 #define SDHCI_SOFTWARE_RESET 0x2F
69 #define SDHCI_RESET_CMD 0x02
70 #define SDHCI_RESET_DATA 0x04
71 #define SDHCI_INT_STATUS 0x30
72 #define SDHCI_INT_RESPONSE BIT(0)
73 #define SDHCI_INT_DATA_END BIT(1)
74 #define SDHCI_INT_ERROR BIT(15)
75 #define SDHCI_SIGNAL_ENABLE 0x38
77 /* RCA assigned by Boot ROM */
78 #define UNIPHIER_EMMC_RCA 0x1000
80 struct uniphier_mmc_cmd {
82 unsigned int resp_type;
87 static int uniphier_emmc_send_cmd(void __iomem *host_base,
88 struct uniphier_mmc_cmd *cmd)
91 u32 mask = SDHCI_INT_RESPONSE;
94 writel(U32_MAX, host_base + SDHCI_INT_STATUS);
95 writel(0, host_base + SDHCI_SIGNAL_ENABLE);
96 writel(cmd->cmdarg, host_base + SDHCI_ARGUMENT);
99 mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN |
100 SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ |
103 writew(mode, host_base + SDHCI_TRANSFER_MODE);
105 if (!(cmd->resp_type & MMC_RSP_PRESENT))
106 flags = SDHCI_CMD_RESP_NONE;
107 else if (cmd->resp_type & MMC_RSP_136)
108 flags = SDHCI_CMD_RESP_LONG;
109 else if (cmd->resp_type & MMC_RSP_BUSY)
110 flags = SDHCI_CMD_RESP_SHORT_BUSY;
112 flags = SDHCI_CMD_RESP_SHORT;
114 if (cmd->resp_type & MMC_RSP_CRC)
115 flags |= SDHCI_CMD_CRC;
116 if (cmd->resp_type & MMC_RSP_OPCODE)
117 flags |= SDHCI_CMD_INDEX;
119 flags |= SDHCI_CMD_DATA;
121 if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data)
122 mask |= SDHCI_INT_DATA_END;
124 writew(SDHCI_MAKE_CMD(cmd->cmdidx, flags), host_base + SDHCI_COMMAND);
127 stat = readl(host_base + SDHCI_INT_STATUS);
128 if (stat & SDHCI_INT_ERROR)
131 } while ((stat & mask) != mask);
136 static int uniphier_emmc_switch_part(void __iomem *host_base, int part_num)
138 struct uniphier_mmc_cmd cmd = {};
140 cmd.cmdidx = MMC_CMD_SWITCH;
141 cmd.resp_type = MMC_RSP_R1b;
142 cmd.cmdarg = (EXT_CSD_PART_CONF << 16) | (part_num << 8) | (3 << 24);
144 return uniphier_emmc_send_cmd(host_base, &cmd);
147 static int uniphier_emmc_is_over_2gb(void __iomem *host_base)
149 struct uniphier_mmc_cmd cmd = {};
150 u32 csd40, csd72; /* CSD[71:40], CSD[103:72] */
153 cmd.cmdidx = MMC_CMD_SEND_CSD;
154 cmd.resp_type = MMC_RSP_R2;
155 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
157 ret = uniphier_emmc_send_cmd(host_base, &cmd);
161 csd40 = readl(host_base + SDHCI_RESPONSE + 4);
162 csd72 = readl(host_base + SDHCI_RESPONSE + 8);
164 return !(~csd40 & 0xffc00380) && !(~csd72 & 0x3);
167 static int uniphier_emmc_load_image(void __iomem *host_base, u32 dev_addr,
168 unsigned long load_addr, u32 block_cnt)
170 struct uniphier_mmc_cmd cmd = {};
173 WARN_ON(load_addr >> 32);
175 writel(load_addr, host_base + SDHCI_DMA_ADDRESS);
176 writew(SDHCI_MAKE_BLKSZ(7, 512), host_base + SDHCI_BLOCK_SIZE);
177 writew(block_cnt, host_base + SDHCI_BLOCK_COUNT);
179 tmp = readb(host_base + SDHCI_HOST_CONTROL);
180 tmp &= ~SDHCI_CTRL_DMA_MASK;
181 tmp |= SDHCI_CTRL_SDMA;
182 writeb(tmp, host_base + SDHCI_HOST_CONTROL);
184 tmp = readb(host_base + SDHCI_BLOCK_GAP_CONTROL);
185 tmp &= ~1; /* clear Stop At Block Gap Request */
186 writeb(tmp, host_base + SDHCI_BLOCK_GAP_CONTROL);
188 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
189 cmd.resp_type = MMC_RSP_R1;
190 cmd.cmdarg = dev_addr;
193 return uniphier_emmc_send_cmd(host_base, &cmd);
196 static int spl_board_load_image(struct spl_image_info *spl_image,
197 struct spl_boot_device *bootdev)
199 u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
200 void __iomem *host_base = (void __iomem *)0x5a000200;
201 struct uniphier_mmc_cmd cmd = {};
205 * deselect card before SEND_CSD command.
206 * Do not check the return code. It fails, but it is OK.
208 cmd.cmdidx = MMC_CMD_SELECT_CARD;
209 cmd.resp_type = MMC_RSP_R1;
211 uniphier_emmc_send_cmd(host_base, &cmd); /* CMD7 (arg=0) */
214 writeb(SDHCI_RESET_CMD | SDHCI_RESET_DATA,
215 host_base + SDHCI_SOFTWARE_RESET);
216 while (readb(host_base + SDHCI_SOFTWARE_RESET))
219 ret = uniphier_emmc_is_over_2gb(host_base);
223 debug("card is block addressing\n");
225 debug("card is byte addressing\n");
229 cmd.cmdarg = UNIPHIER_EMMC_RCA << 16;
231 /* select card again */
232 ret = uniphier_emmc_send_cmd(host_base, &cmd);
234 printf("failed to select card\n");
236 /* Switch to Boot Partition 1 */
237 ret = uniphier_emmc_switch_part(host_base, 1);
239 printf("failed to switch partition\n");
241 ret = uniphier_emmc_load_image(host_base, dev_addr,
242 CONFIG_SYS_TEXT_BASE, 1);
244 printf("failed to load image\n");
248 ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE);
252 ret = uniphier_emmc_load_image(host_base, dev_addr,
253 spl_image->load_addr,
254 spl_image->size / 512);
256 printf("failed to load image\n");
262 SPL_LOAD_IMAGE_METHOD("eMMC", 0, BOOT_DEVICE_BOARD, spl_board_load_image);