2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/errno.h>
12 #include <linux/sizes.h>
17 #define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
18 #define SC_PLLCTRL_SSC_EN BIT(31)
19 #define SC_PLLCTRL2_NRSTDS BIT(28)
20 #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
21 #define SC_PLLCTRL3_REGI_SHIFT 16
22 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
24 /* PLL type: VPLL27 */
25 #define SC_VPLL27CTRL_WP BIT(0)
26 #define SC_VPLL27CTRL3_K_LD BIT(28)
29 #define SC_DSPLLCTRL2_K_LD BIT(28)
31 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
32 unsigned int ssc_rate, unsigned int divn)
37 base = ioremap(reg_base, SZ_16);
41 if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
42 tmp = readl(base); /* SSCPLLCTRL */
43 tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
44 tmp |= (487 * freq * ssc_rate / divn / 512) &
45 SC_PLLCTRL_SSC_DK_MASK;
48 tmp = readl(base + 4);
49 tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
50 tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
55 tmp = readl(base + 4); /* SSCPLLCTRL2 */
56 tmp |= SC_PLLCTRL2_NRSTDS;
57 writel(tmp, base + 4);
64 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
69 base = ioremap(reg_base, SZ_16);
73 tmp = readl(base); /* SSCPLLCTRL */
74 tmp |= SC_PLLCTRL_SSC_EN;
82 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
87 base = ioremap(reg_base, SZ_16);
91 tmp = readl(base + 8); /* SSCPLLCTRL3 */
92 tmp &= ~SC_PLLCTRL3_REGI_MASK;
93 tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
94 writel(tmp, base + 8);
101 int uniphier_ld20_vpll27_init(unsigned long reg_base)
106 base = ioremap(reg_base, SZ_16);
110 tmp = readl(base); /* VPLL27CTRL */
111 tmp |= SC_VPLL27CTRL_WP; /* write protect off */
114 tmp = readl(base + 8); /* VPLL27CTRL3 */
115 tmp |= SC_VPLL27CTRL3_K_LD;
116 writel(tmp, base + 8);
118 tmp = readl(base); /* VPLL27CTRL */
119 tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
127 int uniphier_ld20_dspll_init(unsigned long reg_base)
132 base = ioremap(reg_base, SZ_16);
136 tmp = readl(base + 4); /* DSPLLCTRL2 */
137 tmp |= SC_DSPLLCTRL2_K_LD;
138 writel(tmp, base + 4);