2 * Copyright (C) 2013-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
5 * SPDX-License-Identifier: GPL-2.0+
12 #include "../sc-regs.h"
13 #include "../sg-regs.h"
16 static void upll_init(void)
18 u32 tmp, clk_mode_upll, clk_mode_axosel;
20 tmp = readl(SG_PINMON0);
21 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
22 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
24 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
25 tmp = readl(SC_UPLLCTRL);
27 writel(tmp, SC_UPLLCTRL);
29 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
30 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
31 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
36 /* AXO: default 24.576MHz */
42 writel(tmp, SC_UPLLCTRL);
44 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
46 writel(tmp, SC_UPLLCTRL);
51 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
53 writel(tmp, SC_UPLLCTRL);
56 static void vpll_init(void)
58 u32 tmp, clk_mode_axosel;
60 tmp = readl(SG_PINMON0);
61 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
63 /* set 1 to VPLA27WP and VPLA27WP */
64 tmp = readl(SC_VPLL27ACTRL);
66 writel(tmp, SC_VPLL27ACTRL);
67 tmp = readl(SC_VPLL27BCTRL);
69 writel(tmp, SC_VPLL27BCTRL);
71 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
72 tmp = readl(SC_VPLL27ACTRL3);
74 writel(tmp, SC_VPLL27ACTRL3);
75 tmp = readl(SC_VPLL27BCTRL3);
77 writel(tmp, SC_VPLL27BCTRL3);
79 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
80 tmp = readl(SC_VPLL27ACTRL2);
82 writel(tmp, SC_VPLL27ACTRL2);
83 tmp = readl(SC_VPLL27BCTRL2);
85 writel(tmp, SC_VPLL27BCTRL2);
87 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
88 tmp = readl(SC_VPLL27ACTRL2);
91 writel(tmp, SC_VPLL27ACTRL2);
92 tmp = readl(SC_VPLL27BCTRL2);
95 writel(tmp, SC_VPLL27BCTRL2);
97 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
98 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
100 tmp = readl(SC_VPLL27ACTRL3);
103 writel(tmp, SC_VPLL27ACTRL3);
104 tmp = readl(SC_VPLL27BCTRL3);
107 writel(tmp, SC_VPLL27BCTRL3);
109 /* AXO: default 24.576MHz */
110 tmp = readl(SC_VPLL27ACTRL3);
113 writel(tmp, SC_VPLL27ACTRL3);
114 tmp = readl(SC_VPLL27BCTRL3);
117 writel(tmp, SC_VPLL27BCTRL3);
120 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
121 tmp = readl(SC_VPLL27ACTRL3);
123 writel(tmp, SC_VPLL27ACTRL3);
124 tmp = readl(SC_VPLL27BCTRL3);
126 writel(tmp, SC_VPLL27BCTRL3);
131 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
132 tmp = readl(SC_VPLL27ACTRL2);
134 writel(tmp, SC_VPLL27ACTRL2);
135 tmp = readl(SC_VPLL27BCTRL2);
137 writel(tmp, SC_VPLL27BCTRL2);
139 /* set 0 to VPLA27WP and VPLA27WP */
140 tmp = readl(SC_VPLL27ACTRL);
142 writel(tmp, SC_VPLL27ACTRL);
143 tmp = readl(SC_VPLL27BCTRL);
145 writel(tmp, SC_VPLL27BCTRL);
148 void uniphier_ld4_pll_init(void)
152 uniphier_ld4_dpll_ssc_en();