2 * Copyright (C) 2013-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/delay.h>
12 #include "../sc-regs.h"
13 #include "../sg-regs.h"
16 static void vpll_init(void)
18 u32 tmp, clk_mode_axosel;
20 /* Set VPLL27A & VPLL27B */
21 tmp = readl(SG_PINMON0);
22 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
24 /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
25 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
26 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
29 /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
30 tmp = readl(SC_VPLL27ACTRL);
32 writel(tmp, SC_VPLL27ACTRL);
33 tmp = readl(SC_VPLL27BCTRL);
35 writel(tmp, SC_VPLL27BCTRL);
37 /* Unset VPLA_K_LD and VPLB_K_LD bit */
38 tmp = readl(SC_VPLL27ACTRL3);
40 writel(tmp, SC_VPLL27ACTRL3);
41 tmp = readl(SC_VPLL27BCTRL3);
43 writel(tmp, SC_VPLL27BCTRL3);
45 /* Set VPLA_M and VPLB_M to 0x20 */
46 tmp = readl(SC_VPLL27ACTRL2);
49 writel(tmp, SC_VPLL27ACTRL2);
50 tmp = readl(SC_VPLL27BCTRL2);
53 writel(tmp, SC_VPLL27BCTRL2);
55 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
56 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
57 /* Set VPLA_K and VPLB_K for AXO: 25MHz */
58 tmp = readl(SC_VPLL27ACTRL3);
61 writel(tmp, SC_VPLL27ACTRL3);
62 tmp = readl(SC_VPLL27BCTRL3);
65 writel(tmp, SC_VPLL27BCTRL3);
67 /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
68 tmp = readl(SC_VPLL27ACTRL3);
71 writel(tmp, SC_VPLL27ACTRL3);
72 tmp = readl(SC_VPLL27BCTRL3);
75 writel(tmp, SC_VPLL27BCTRL3);
81 /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
82 tmp = readl(SC_VPLL27ACTRL3);
84 writel(tmp, SC_VPLL27ACTRL3);
85 tmp = readl(SC_VPLL27BCTRL3);
87 writel(tmp, SC_VPLL27BCTRL3);
89 /* Unset VPLA_SNRST and VPLB_SNRST bit */
90 tmp = readl(SC_VPLL27ACTRL2);
92 writel(tmp, SC_VPLL27ACTRL2);
93 tmp = readl(SC_VPLL27BCTRL2);
95 writel(tmp, SC_VPLL27BCTRL2);
97 /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
98 tmp = readl(SC_VPLL27ACTRL);
100 writel(tmp, SC_VPLL27ACTRL);
101 tmp = readl(SC_VPLL27BCTRL);
103 writel(tmp, SC_VPLL27BCTRL);
106 void uniphier_pro4_pll_init(void)
109 uniphier_ld4_dpll_ssc_en();